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PDF CY7C374 Data sheet ( Hoja de datos )
| Número de pieza | CY7C374 | |
| Descripción | 128-Macrocell Flash CPLD | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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For new designs see CY7C374i
CY7C374
UltraLogic™ 128-Macrocell Flash CPLD
Features
Functional Description
• 128 macrocells in eight logic blocks
• 64 I/O pins
• 6 dedicated inputs including 4 clock pins
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
• High speed
— fMAX = 100 MHz
— tPD = 12 ns
— tS = 6 ns
— tCO = 7 ns
• Electrically Alterable Flash technology
• Available in 84-pin PLCC, 84-pin CLCC, 100-pin TQFP,
and 84-pin PGA packages
• Pin compatible with the CY7C373
The CY7C374 is a Flash erasable Complex Programmable
Logic Device (CPLD) and is part of the FLASH370 family of
high-density, high-speed CPLDs. Like all members of the
FLASH370 family, the CY7C374 is designed to bring the ease
of use and high performance of the 22V10 to high-density
CPLDs.
The 128 macrocells in the CY7C374 are divided between eight
logic blocks. Each logic block includes 16 macrocells, a 72 x
86 product term array, and an intelligent product term allocator.
The logic blocks in the FLASH370 architecture are connected
with an extremely fast and predictable routing resource—the
Programmable Interconnect Matrix (PIM). The PIM brings flex-
ibility, routability, speed, and a uniform delay to the intercon-
nect.
The CY7C374 is a register intensive 128-Macrocell CPLD. Ev-
ery two macrocells in the device feature an associated I/O pin,
resulting in 64 I/O pins on the CY7C374. In addition, there are
two dedicated inputs and four input/clock pins.
Logic Block Diagram
CLOCK
INPUTS INPUTS
8 I/Os
I/O0−I/O7
8 I/Os
I/O8−I/O15
8 I/Os
I/O16−I/O23
8 I/Os
I/O24−I/O31
.comSelection Guide
t4uMaximum Propagation Delay tPD (ns)
eMinimum Set-Up, tS (ns)
heMaximum Clock to Output, tCO (ncs)
sMaximum Supply
taCurrent, ICC (mA)
.daCypress Semiconductor Corporation
wwwDocument #: 38-03021 Rev. **
2
INPUT
MACROCELLS
4
LOGIC
BLOCK
A
36
16
PIM
LOGIC
BLOCK
B
36
16
LOGIC
BLOCK
C
36
16
LOGIC
BLOCK
D
32
36
16
4
INPUT/CLOCK
MACROCELLS
4
LOGIC
36 BLOCK
16 H
LOGIC
36 BLOCK
16 G
LOGIC
36 BLOCK
F
16
LOGIC
36 BLOCK
E
16
32
8 I/Os
I/O56−I/O63
8 I/Os
I/O48−I/O55
8 I/Os
I/O40−I/O47
8 I/Os
I/O32−I/O39
7C374–1
Commercial
Military/Industrial
7C374-100
12
6
7
300
7C374-83
15
8
8
300
370
7C374-66
20
10
10
300
370
7C374L-66
20
10
10
150
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Revised April 1998
1 page  
CY7C374
AC Test Loads and Waveforms
238Ω (COM’L)
319Ω (MIL)
5V
238Ω (COM'L)
319Ω (MIL)
5V 3.0V
OUTPUT
35 pF
INCLUDING
JIG AND
SCOPE
(a)
OUTPUT
170Ω (COM’L)
236Ω (MIL)
5 pF
INCLUDING
JIG AND
SCOPE
(b)
170Ω (COM'L)
236Ω (MIL)
GND
10%
≤2 ns
7C374–5
Equivalent to:
OUTPUT
THÉVENIN EQUIVALENT
99Ω (COM’L)
136Ω (MIL) 2.08V (COM'L)
2.13V (MIL)
ALL INPUT PULSES
90%
90%
10%
≤ 2n
7C374–6
Parameter[9]
tER(−)
VX
1.5V
Output Waveform Measurement Level
VOH
−0.5V
tER(+)
tEA(+)
tEA(−)
2.6V
1.5V
Vthc
VOH
−0.5V
−0.5V
VX
VX
−0.5V
Note:
9. tER is measured with 5-pF AC Test Load and tEA is measured with 35-pF AC Test Load.
VX
VX
VOH
VOH
Document #: 38-03021 Rev. **
Page 5 of 16
5 Page 
Switching Waveforms (continued)
Output Enable/Disable
INPUT
OUTPUTS
tER
tEA
Ordering Information
Speed
(MHz)
100
83
66
Ordering Code
CY7C374-100AC
CY7C374-100GC
CY7C374-100JC
CY7C374-83AC
CY7C374-83GC
CY7C374-83JC
CY7C374-83AI
CY7C374-83JI
CY7C374-83GMB
CY7C374-83YMB
CY7C374-66AC
CY7C374-66GC
CY7C374-66JC
CY7C374-66AI
CY7C374-66JI
CY7C374-66GMB
CY7C374-66YMB
CY7C374L-66AC
CY7C374L-66JC
Package
Name
Package Type
Operating
Range
A100 100-Pin Thin Quad Flat Pack
Commercial
G84 84-Pin Grid Array (Cavity Up)
J83 84-Lead Plastic Leaded Chip Carrier
A100 100-Pin Thin Quad Flat Pack
Commercial
G84 84-Pin Grid Array (Cavity Up)
J83 84-Lead Plastic Leaded Chip Carrier
A100 100-Pin Thin Quad Flat Pack
Industrial
J83 84-Lead Plastic Leaded Chip Carrier
G84 84-Pin Grid Array (Cavity Up)
Military
Y84 84-Pin Ceramic Leaded Chip Carrier
A100 100-Pin Thin Quad Flat Pack
Commercial
G84 84-Pin Grid Array (Cavity Up)
J83 84-Lead Plastic Leaded Chip Carrier
A100 100-Pin Thin Quad Flat Pack
Industrial
J83 84-Lead Plastic Leaded Chip Carrier
G84 84-Pin Grid Array (Cavity Up)
Military
Y84 84-Pin Ceramic Leaded Chip Carrier
A100 100-Pin Thin Quad Flat Pack
Commercial
J83 84-Lead Plastic Leaded Chip Carrier
CY7C374
7C374–17
Document #: 38-03021 Rev. **
Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet CY7C374.PDF ] | |
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