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PDF SSM-2120 Data sheet ( Hoja de datos )

Número de pieza SSM-2120
Descripción (SSM-2122) Dynamic Range Processors/Dual VCA
Fabricantes Analog 
Logotipo Analog Logotipo



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No Preview Available ! SSM-2120 Hoja de datos, Descripción, Manual

a
FEATURES
0.01% THD at +10 dBV In/Out
100 dB VCA Dynamic Range
Low VCA Control Feedthrough
100 dB Level Detection Range
Log/Antilog Control Paths
Low External Component Count
APPLICATIONS
Compressors
Expanders
Limiters
AGC Circuits
Voltage-Controlled Filters
Noise Reduction Systems
Stereo Noise Gates
Dynamic Range
Processors/Dual VCA
SSM2120/SSM2122
FUNCTIONAL BLOCK DIAGRAM
V+
CURRENT
MIRRORS
SIGNAL
OUT
36k
–VC
+VC
V+
V+
SIGNAL
INPUT 36k
V+
IREF
GENERAL DESCRIPTION
The SSM2120 is a monolithic integrated circuit designed for the
purpose of processing dynamic signals in various analog systems
including audio. This “dynamic range processor” consists of two
VCAs and two level detectors (the SSM2122 consists of two
VCAs only). These circuit blocks allow the user to logarithmically
control the gain or attenuation of the signals presented to the
level detectors depending on their magnitudes. This allows the
compression, expansion or limiting of ac signals, some of the
primary applications for the SSM2120.
V–
PIN CONNECTIONS
22-Pin Plastic DIP
(P Suffix)
16-Pin Plastic DIP
(P Suffix)
THRESH 1 1
22 GND
LOG AV 1 2
21 V+
CONOUT 1 3
20 SIGOUT 2
SIGOUT 1 4
19 +VC2
+VC1 5 SSM2120 18 CFT 2
CFT 1 6 TOP VIEW 17 –VC2
–VC1 7 (Not to Scale) 16 SIGIN 2
SIGIN 1 8
15 RECIN 2
RECIN 1 9
14 CONOUT 2
IREF 10
13 LOG AV 2
V– 11
12 THRESH 2
GND 1
16 GND
SIGOUT 1 2
15 V+
+VC1 3
14 SIGOUT 2
CFT 1 4 SSM2122 13 +VC2
TOP VIEW
–VC1 5 (Not to Scale) 12 CFT 2
SIGIN 1 6
11 –VC2
IREF 7
10 SIGIN 2
V– 8
9 GND
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703

1 page




SSM-2120 pdf
2V
100
90
1s
10
0%
Figure 4. Detector Output
2V
100
90
SSM2120/SSM2122
The decay rates are linear ramps that are dependent on the
current out of the LOG AV pin (set by RREF) and the value of
CAV. The integration or decay time of the circuit is derived from
the formula:
Decrementation Rate (in dB/s) =
IREF × 333
C AV
Table I. Settling Time (tS) for CAV = 10 F. tS = tS (CAV = 10 F)
5 dB
3 dB
2 dB
1 dB
10 dB Step
20 dB Step
30 dB Step
40 dB Step
50 dB Step
60 dB Step
11.28 ms
16.65
18.15
18.61
21.46
26.83
28.33
27.79
30.19
35.56
37.06
37.52
(+144 µs)
(+46 µs)
46.09
51.46
52.96
53.42
10
0%
50ms
Figure 5. Overlayed Detector Output
DYNAMIC ATTACK AND DECAY RATES
Figure 5 shows the output levels overlayed using a storage
scope. The attack rate is determined by the step size and the
value of CAV. The attack time to final value is a function of the
step size increase. Table I shows the values of total settling
times to within 5 dB, 3 dB, 2 dB and 1 dB of final value with
CAV = 10 µF. When step sizes exceed 40 dB, the increase in
settling time for larger steps is negligible. To calculate the attack
time to final value for any value of CAV, simply multiply the
value in the chart by CAV/10 µF.
APPLICATIONS
The following applications for the SSM2120 use both the VCAs
and level detectors in conjunction to assimilate a variety of
functions.
The first section describes the arrangement of the threshold
control in each control circuit configuration. These control
circuits form the foundation for the applications to follow which
include the downward expander, compressor/limiter and
compandor.
THRESHOLD CONTROL
Figure 6a shows the control circuit for a typical downward
expander while Figure 6b shows a typical control curve. Here,
the threshold potentiometer adjusts VT to provide a negative
unipolar control output. This is typically used in noise gate,
downward expander, and dynamic filter applications. This
potentiometer is used in all applications to control the signal
level versus control voltage characteristics.
RIN
L
MONO
OR R
RIN
RECIN
RLL
MONO – RIN = 10k
STEREO – RIN = 20k
2V
THRESHOLD
CONTROL
|IIN|
VT
V+ V–
RT
39kCONOUT RCON
1k
LOG AV
CAV
1.5M
V–
TO +VC
200
V–
THRESHOLD
+
* *LOWER LIMIT CAN BE FIXED
BY CONNECTING A RESISTOR
RLL FROM RECIN TO GROUND
VIN – dB
a. Control Circuit
b. Typical Downward Expander
Control Curve
Figure 6. Noise Gate/Downward Expander Control Circuit and Typical Response
REV. C
–5–

5 Page





SSM-2120 arduino
SSM2120/SSM2122
FADER AUTOMATION
The SSM2120 can be used in fader automation systems to serve
two channels. The inverting control port is connected through
an attenuator to the VCA control voltage source. The noninverting
control port is connected to a control circuit (such as Figure 6)
which senses the input signal level to the VCA. Above the
threshold voltage, which can be set quite low (for example
–60 dBV), the VCA operates at its programmed gain. Below
this threshold the VCA will downward expand at a rate deter-
mined by the +VC control port attenuator. By keeping the release
time constant in the 10 ms to 25 ms range, the modulation of
the VCA standing noise floor (–80 dB at unity-gain), can be
kept inaudibly low.
The SSM2300 8-channel multiplexed sample-and-hold IC
makes an excellent controller for VCAs in automation systems.
Figure 16 shows the basic connection for the SSM2122 operating
as a unity-gain VCA with its noninverting control ports grounded
and access to the inverting control ports. This is typical for fader
automation applications. Since this device is a pinout option of
the SSM2120, the VCAs will behave exactly as described
earlier in the VCA section.
The SSM2122 can also be used with two or more op amps to
implement complex voltage-controlled filter functions. Biquad
and state-variable two-pole filters offering low pass, bandpass
and high pass outputs can be realized. Higher order filters can
also be formed by connecting two or more such stages in series.
10pF
+15V
0.1µF
36k
1 16
10pF
SIGOUT 1
1/2
TL082
V+
200
2
3
15
14
50k*
–VC1
SIGIN 1
V–
36k
220k
200
4 13
SSM2122
5 12
6 11
2000pF
150k
47V+
7
0.1µF
10
89
200
220k
200
36k
1/2
TL082
V+
SIGOUT 2
50k*
V–
36k
2000pF
47
–VC2
SIGIN 2
–15V
*OPTIONAL CONTROL FEEDTHROUGH TRIM
Figure 16. SSM2122 Basic Connection (Control Ports at 0 V)
REV. C
–11–

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