PDF IC41C16100A Data sheet ( Hoja de datos )

Número de pieza	IC41C16100A
Descripción	1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
Fabricantes	ICSI
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No Preview Available ! IC41C16100A/IC41C16100AS IC41LV16100A/IC41LV16100AS Document Title 1M x 16 bit Dynamic RAM with EDO Page Mode Revision History Revision No 0A History Initial Draft Draft Date Remark September 28,2001 Integrated Circuit Solution Inc. DR030-0A 09/28/2001 1 1 page IC41C16100A/IC41C16100AS IC41LV16100A/IC41LV16100AS Functional Description The IC41C16100A(S) and IC41LV16100A(S) is a CMOS DRAM optimized for high-speed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 16 address bits. These are entered ten bits (A0-A9) at a time. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first ten bits and CAS is used the latter ten bits. The IC41C16100A(S) and IC41LV16100A(S) has two CAS controls, LCAS and UCAS. The LCAS and UCAS inputs internally generates a CAS signal functioning in an iden- tical manner to the single CAS input on the other 1M x 16 DRAMs. The key difference is that each CAS controls its corresponding I/O tristate logic (in conjunction with OE and WE and RAS). LCAS controls I/O0 through I/O7 and UCAS controls I/O8 through I/O15. The IC41C16100A(S) and IC41LV16100A(S) CAS func- tion is determined by the first CAS (LCAS or UCAS) transitioning LOW and the last transitioning back HIGH. The two CAS controls give the IC41C16100A(S) and IS41LV16100A(S) both BYTE READ and BYTE WRITE cycle capabilities. Memory Cycle A memory cycle is initiated by bring RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP, tCP has elapsed. Read Cycle A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA, tCAC and tOEA are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters. Write Cycle A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs first. Refresh Cycle To retain data, 1,024 refresh cycles are required in each 16 ms period. There are two ways to refresh the memory. 1. By clocking each of the 1,024 row addresses (A0 through A9) with RAS at least once every 16 ms. Any read, write, read-modify-write or RAS-only cycle re- freshes the addressed row. 2. Using a CAS-before-RAS refresh cycle. CAS-before- RAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh Integrated Circuit Solution Inc. DR030-0A 09/28/2001 cycle, an internal 10-bit counter provides the row ad- dresses and the external address inputs are ignored. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. Self Refresh Cycle The Self Refresh allows the user a dynamic refresh, data retention mode at the extended refresh period of 128 ms. i.e., 125 µs per row when using distributed CBR refreshes. The feature also allows the user the choice of a fully static, low power data retention mode. The optional Self Refresh feature is initiated by performing a CBR Refresh cycle and holding RAS LOW for the specified tRASS. The Self Refresh mode is terminated by driving RAS HIGH for a minimum time of tRPS. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the RAS LOW-to-HIGH transition. If the DRAM controller uses a distributed refresh sequence, a burst refresh is not required upon exiting Self Refresh. However, if the DRAM controller utilizes a RAS-only or burst refresh sequence, all 1,024 rows must be refreshed within the average internal refresh rate, prior to the re- sumption of normal operation. Extended Data Out Page Mode EDO page mode operation permits all 1,024 columns within a selected row to be randomly accessed at a high data rate. In EDO page mode read cycle, the data-out is held to the next CAS cycle’s falling edge, instead of the rising edge. For this reason, the valid data output time in EDO page mode is extended compared with the fast page mode. In the fast page mode, the valid data output time becomes shorter as the CAS cycle time becomes shorter. Therefore, in EDO page mode, the timing margin in read cycle is larger than that of the fast page mode even if the CAS cycle time becomes shorter. In EDO page mode, due to the extended data function, the CAS cycle time can be shorter than in the fast page mode if the timing margin is the same. The EDO page mode allows both read and write opera- tions during one RAS cycle, but the performance is equivalent to that of the fast page mode in that case. Power-On After application of the VCC supply, an initial pause of 200 µs is required followed by a minimum of eight initial- ization cycles (any combination of cycles containing a RAS signal). During power-on, it is recommended that RAS track with VCC or be held at a valid VIH to avoid current surges. 5 5 Page IC41C16100A/IC41C16100AS IC41LV16100A/IC41LV16100AS READ CYCLE RAS tCRP UCAS/LCAS tRAS tRC tRCD tCSH tRSH tCAS tRP tRRH tASR ADDRESS WE I/O OE Row tRAD tRAH tASC tRAL Column tRCS tCAH tRCH Row Open tAA tRAC tCAC tCLZ tOE tOFF(1) Valid Data Open tOD tOES Undefined Don’t Care Note: 1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. Integrated Circuit Solution Inc. DR030-0A 09/28/2001 11 11 Page

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