PDF ST10F280 Data sheet ( Hoja de datos )

Número de pieza	ST10F280
Descripción	16-BIT MCU WITH MAC UNIT / 512K BYTE FLASH MEMORY AND 18K BYTE RAM
Fabricantes	ST Microelectronics
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ST10F280 16-BIT MCU WITH MAC UNIT, 512K BYTE FLASH MEMORY AND 18K BYTE RAM s HIGH PERFORMANCE CPU WITH DSP FUNCTIONS - 16-BIT CPU WITH 4-STAGE PIPELINE. - 50ns INSTRUCTION CYCLE TIME AT 40MHz CPU CLOCK. - MULTIPLY/ACCUMULATE UNIT (MAC) 16 X 16-BIT MULTIPLICATION, 40-BIT ACCUMULATOR - REPEAT UNIT. - ENHANCED BOOLEAN BIT MANIPULATION FACILITIES. - ADDITIONAL INSTRUCTIONS TO SUPPORT HLL AND OPERATING SYSTEMS. - SINGLE-CYCLE CONTEXT SWITCHING SUPPORT. s MEMORY ORGANIZATION - 512K BYTE ON-CHIP FLASH MEMORY SINGLE VOLTAGE WITH ERASE/PROGRAM CONTROLLER. - 100K ERASING/PROGRAMMING CYCLES. - 20 YEAR DATA RETENTION TIME - UP TO 16M BYTE LINEAR ADDRESS SPACE FOR CODE AND DATA (5M BYTE WITH CAN). - 2K BYTE ON-CHIP INTERNAL RAM (IRAM). - 16K BYTE EXTENSION RAM (XRAM). s FAST AND FLEXIBLE BUS - PROGRAMMABLE EXTERNAL BUS CHARACTERIS- TICS FOR DIFFERENT ADDRESS RANGES. - 8-BIT OR 16-BIT EXTERNAL DATA BUS. - MULTIPLEXED OR DEMULTIPLEXED EXTERNAL ADDRESS/DATA BUSES. - FIVE PROGRAMMABLE CHIP-SELECT SIGNALS. - HOLD-ACKNOWLEDGE BUS ARBITRATION SUPPORT. s INTERRUPT - 8-CHANNEL PERIPHERAL EVENT CONTROLLER FOR SINGLE CYCLE, INTERRUPT DRIVEN DATA TRANSFER. - 16-PRIORITY-LEVEL INTERRUPT SYSTEM WITH 56 SOURCES, SAMPLE-RATE DOWN TO 25ns. s TWO MULTI-FUNCTIONAL GENERAL PURPOSE TIMER UNITS WITH 5 TIMERS. s TWO 16-CHANNEL CAPTURE/COMPARE UNITS s A/D CONVERTER - 2X16-CHANNEL 10-BIT. - 4.85µS CONVERSION TIME - ONE TIMER FOR ADC CHANNEL INJECTION s 8-CHANNEL PWM UNIT s SERIAL CHANNELS - SYNCHRONOUS/ASYNC SERIAL CHANNEL - HIGH-SPEED SYNCHRONOUS CHANNEL. s FAIL-SAFE PROTECTION - PROGRAMMABLE WATCHDOG TIMER. - OSCILLATOR WATCHDOG. PRODUCT PREVIEW PBGA208 (23 x 23 x 1.96 - Pitch 1.27 mm) (Plastic Bold Grid Array) ORDER CODE: ST10F280-JT3 s TWO CAN 2.0b INTERFACES OPERATING ON ONE OR TWO CAN BUSSES (30 OR 2X15 MESSAGE OBJECTS) s ON-CHIP BOOTSTRAP LOADER s CLOCK GENERATION - ON-CHIP PLL. - DIRECT OR PRESCALED CLOCK INPUT. s UP TO 143 GENERAL PURPOSE I/O LINES - INDIVIDUALLY PROGRAMMABLE AS INPUT, OUT- PUT OR SPECIAL FUNCTION. - PROGRAMMABLE THRESHOLD (HYSTERESIS). s IDLE AND POWER DOWN MODES s MAXIMUM CPU FREQUENCY 40MHz s PACKAGE PBGA 208 BALLS (23mm x 23mm x 1.96 mm - PITCH 1.27mm). s SINGLE VOLTAGE SUPPLY: 5V ±10% (EMBEDDED REGULATOR FOR 3.3 V CORE SUPPLY). s TEMPERATURE RANGE: -40 +125°C 512K Byte Flash Memory 32 CPU-Core and MAC Unit 16K Byte XRAM P4.5 CAN1_RxD P4.6 CAN1_TxD P4.4 CAN2_RxD P4.7 CAN2_TxD CAN1 CAN2 16 16 PEC Interrupt Controller 16 16 2K Byte Internal RAM Watchdog Oscillator and PLL XTAL1 XTAL2 16 3.3V Voltage Regulator 16 16 8 Port 6 8 Port 5 16 BRG BRG Port 3 15 16 Port 7 Port 8 88 P7.7 Trigger for ADC channel injection XPORT10 XPORT9 XPWM XTIMER 16 16 4 XADCINJ External connexion March 2003 This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/186 1 page ST10F280 17.3 - 17.4 - 17.5 - 17.6 - SOFTWARE RESET .................................................................................................. WATCHDOG TIMER RESET ..................................................................................... RSTOUT PIN AND BIDIRECTIONAL RESET ............................................................ RESET CIRCUITRY ................................................................................................... 131 131 131 132 18 - 18.1 - 18.2 - 18.2.1 - 18.2.2 - 19 - 19.1 - 19.2 - POWER REDUCTION MODES ................................................................................. IDLE MODE ................................................................................................................ POWER DOWN MODE .............................................................................................. Protected Power Down Mode ..................................................................................... Interruptable Power Down Mode ................................................................................ SPECIAL FUNCTION REGISTER OVERVIEW ......................................................... IDENTIFICATION REGISTERS ................................................................................. SYSTEM CONFIGURATION REGISTERS ................................................................ 135 135 135 136 136 139 148 149 20 - ELECTRICAL CHARACTERISTICS ......................................................................... 20.1 - ABSOLUTE MAXIMUM RATINGS ............................................................................. 20.2 - PARAMETER INTERPRETATION ............................................................................. 20.3 - 20.3.1 - 20.3.2 - DC CHARACTERISTICS ........................................................................................... A/D Converter Characteristics .................................................................................... Conversion Timing Control ....................................................................................... 20.4 - 20.4.1 - 20.4.2 - 20.4.3 - 20.4.4 - 20.4.5 - 20.4.6 - 20.4.7 - 20.4.8 - 20.4.9 - 20.4.10 - 20.4.11 - 20.4.12 - 20.4.13 - 20.4.14 - 20.4.14.1 20.4.14.2 AC CHARACTERISTICS ............................................................................................ Test Waveforms ....................................................................................................... Definition of Internal Timing ........................................................................................ Clock Generation Modes ............................................................................................ Prescaler Operation .................................................................................................... Direct Drive ................................................................................................................. Oscillator Watchdog (OWD) ....................................................................................... Phase Locked Loop .................................................................................................... External Clock Drive XTAL1 ....................................................................................... Memory Cycle Variables ............................................................................................. Multiplexed Bus .......................................................................................................... Demultiplexed Bus ...................................................................................................... CLKOUT and READY ................................................................................................. External Bus Arbitration .............................................................................................. High-Speed Synchronous Serial Interface (SSC) Timing ........................................... Master Mode................................................................................................................ Slave mode.................................................................................................................. 155 155 155 155 158 159 160 160 160 161 162 162 162 162 163 164 165 171 177 179 181 181 182 21 - PACKAGE MECHANICAL DATA ........................................................................... 183 22 - ORDERING INFORMATION ...................................................................................... 184 5/186 5 Page ST10F280 Table 1 : Ball Description (continued) Symbol P3.0 - P3.13, P3.15 P4.0 – P4.7 Ball Number Type Function R12 T13 P12 R13 T14 P13 R14 P14 R15 R16 N14 P15 P16 M14 T17 N16 M15 L14 M16 L15 L16 K14 K15 I/O Port 3 is a 15-bit (P3.14 is missing) bidirectional I/O port. It is bit-wise program- mable for input or output via direction bits. For a pin configured as input, the out- put driver is put into high-impedance state. Port 3 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or special). The following Port 3 pins also serve for alternate functions: I P3.0 T0IN CAPCOM Timer T0 Count Input O P3.1 T6OUT GPT2 Timer T6 Toggle Latch Output I P3.2 CAPIN GPT2 Register CAPREL Capture Input O P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output I P3.4 T3EUD GPT1 Timer T3 External Up / Down Control Input I P3.5 T4IN GPT1 Timer T4 Input for Count / Gate / Reload / Capture I P3.6 T3IN GPT1 Timer T3 Count / Gate Input I P3.7 T2IN GPT1 Timer T2 Input for Count / Gate / Reload / Capture I/O P3.8 MRST SSC Master-Receive / Slave-Transmit I/O I/O P3.9 MTSR SSC Master-Transmit / Slave-Receive O/I I/O P3.10 TxD0 ASC0 Clock / Data Output (Asynchronous / Synchronous) O P3.11 RxD0 ASC0 Data Input (Asynchronous) or I/O (Synchronous) O P3.12 BHE WRH External Memory High Byte Enable Signal, External Memory High Byte Write Strobe I/O P3.13 SCLK SSC Master Clock Output / Slave Clock Input O P3.15 CLKOUT System Clock Output (=CPU Clock) I/O Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. The input threshold is selectable (TTL or special). P4.6 & P4.7 outputs can be configured as push-pull or open-drain drivers. In case of an external bus configuration, Port 4 can be used to output the seg- ment address lines: O P4.0 A16 Least Significant Segment Address Line O P4.1 A17 Segment Address Line O P4.2 A18 Segment Address Line O P4.3 A19 Segment Address Line O P4.4 A20 Segment Address Line I CAN2_RxD CAN2 Receive Data Input O P4.5 A21 Segment Address Line I CAN1_RxD CAN1 Receive Data Input O P4.6 O A22 Segment Address Line, CAN_TxD CAN1_TxD CAN1 Transmit Data Output O P4.7 A23 Most Significant Segment Address Line O CAN2_TxD CAN2 Transmit Data Output 11/186 11 Page

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