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PDF LTC1283C Data sheet ( Hoja de datos )
| Número de pieza | LTC1283C | |
| Descripción | 3V Single Chip 10-Bit Data Acquisition System | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
s Single Supply 3.3V or ±3.3V Operation
s Software Programmable Features:
Unipolar/Bipolar Conversions
4 Differential/8 Single-Ended Inputs
MSB- or LSB-First Data Sequence
Variable Data Word Length
s Built-In Sample-and-Hold
s Direct 4-Wire Interface to Most MPU Serial Ports
and all MPU Parallel Ports
s 15kHz Maximum Throughput Rate
KEY SPECIFICATIO S
s Minimum Guaranteed Supply Voltage: 3V
s Resolution: 10 Bits
s Offset Error: ±0.5LSB Max
s Linearity Error: ±0.5LSB Max
s Gain Error (LTC1283A): ±1LSB Max
s Conversion Time: 44µs
s Supply Current: 350µA Max, 150µA Typ
TYPICAL APPLICATI
4.7µF
3V
FOR 83CL410 CODE SEE
APPLICATIONS INFORMATION SECTION
LTC1283
DIFFERENTIAL
INPUT
MPU
(e.g., 83CL410)
3V
–3V
3V
T
BIPOLAR
INPUT
DOUT
DIN
SCLK
UNIPOLAR CS
INPUTS
SERIAL DATA LINK
P1.1
P1.2
P1.3
P1.4
(+)
(–)
–UNIPOLAR
INPUT
–3V
LTC1283 • TA01
LTC1283
3V Single Chip 10-Bit Data
Acquisition System
DESCRIPTIO
The LTC1283 is a 3V data acquisition component which
contains a serial I/O successive approximation A/D con-
verter. It uses LTCMOSTM switched capacitor technology
to perform either 10-bit unipolar, or 9-bit plus sign bipolar
A/D conversions. The 8-channel input multiplexer can be
configured for either single-ended or differential inputs (or
combinations thereof). An on-chip sample-and-hold is
included for all single-ended input channels.
The serial I/O is designed to be compatible with industry-
standard full-duplex serial interfaces. It allows either MSB-
or LSB-first data and automatically provides 2’s comple-
ment output coding in the bipolar mode. The output data
word can be programmed for a length of 8-, 10-, 12-, or
16-bit. This allows easy interface to shift registers and a
variety of processors.
Both the LTC1283A and LTC1283 are specified with offset
and linearity errors less than ±0.5LSB. The LTC1283A has
a gain error limit of ±1LSB. The 1283 is specified with a
gain error limit of ±2LSB for applications where gain is
adjustable or less critcial.
LTCMOS is a trademark of Linear Technology Corp.
1.0
0.5
0
–0.5
– 1.0
0
Linearity Plot
512
OUTPUT CODE
1024
LTC1283 • TA02
1
1 page  
LTC1283
TYPICAL PERFOR A CE CHARACTERISTICS
Change in Full-Scale Error
vs Reference Voltage
1.0
0.9
VCC = 3V
ACLK = 500kHz
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0 0.5 1.0 1.5 2.0 2.5
REFERENCE VOLTAGE (V)
LTC1283 • G04
Change in Linearity Error
vs Temperature
0.5
VCC = 3V
VREF = 2.5V
0.4 ACLK = 500kHz
0.3
0.2
0.1
0
–50 –25 0 25 50 75 100 125
AMBIENT TEMPERATURE (°C)
LTC1283 • G07
Maximum Conversion Clock Rate
vs Reference Voltage
1500
VCC = 3V
1250
1000
Linearity Error
vs Reference Voltage
1.0
0.9
VCC = 3V
ACLK = 500kHz
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0 0.5 1.0 1.5 2.0 2.5
REFERENCE VOLTAGE (V)
LTC1283 • G05
Change in Gain Error
vs Temperature
0.5
VCC = 3V
VREF = 2.5V
0.4 ACLK = 500kHz
0.3
0.2
0.1
0
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
LTC1283 • G08
Maximum Conversion Clock Rate
vs Source Resistance
1500
VCC = 3V
1250
1000
Change in Offset Error
vs Temperature
0.5
VCC = 3V
VREF = 2.5V
0.4 ACLK = 500kHz
0.3
0.2
0.1
0
–50 –25 0 25 50 75 100 125
AMBIENT TEMPERATURE (°C)
LTC1283 • G06
Maximum Conversion Clock Rate
vs Temperature
2.0
VCC = 3V
1.75 VREF = 2.5V
1.5
1.25
1.0
0.75
0.5
0.25
0
–50 –25 0 25 50 75 100 125
AMBIENT TEMPERATURE (˚C)
LTC1283 • G09
Maximum Filter Resistor
vs Cycle Time
100k
10k
RFILTER
VIN
CFILTER ≥ 1µF
+
–
VCC = 3V
750 750 1k
VIN + INPUT
500 500
– INPUT
100
250 250 RSOURCE–
0
0 0.5 1.0 1.5 2.0 2.5
0
1
10
10
100
10
100
1000
10000
REFERENCE VOLTAGE (V)
LTC1283 • G10
RSOURCE (kΩ)
LTC1283 • G11
CYCLE TIME (µs)
LTC1283 • G12
*Maximum ACLK frequency represents the ACLK frequency at which a 0.1LSB shift in the error at
any code transition from its 100kHz value is first detected.
**Maximum RFILTER represents the filter resistor value at which a 0.1LSB change in full-scale error
from its value at RFILTER = 0 is first detected.
5
5 Page 
LTC1283
APPLICATI S I FOR ATIO
MSB-First/LSB-First Format (MSBF)
The output data of the LTC1283 is programmed for MSB-
first or LSB-first sequence using the MSBF bit. For MSB-
first output data the input word clocked to the LTC1283
should always contain a logical one in the sixth bit location
(MSBF bit). Likewise for LSB-first output data, the input
word clocked to the LTC1283 should always contain a zero
in the MSBF bit location. The MSBF bit in a given DIN word
will control the order of the next DOUT word. The MSBF bit
affects only the order of the output data word. The order
of the input word is unaffected by this bit.
MSBF
0
1
Word Length (WL1, WL0)
OUTPUT FORMAT
LSB-First
MSB-First
LTC1283 AI08
The last two bits of the input word (WL1 and WL0)
program the output data word length of the LTC1283.
Word lengths of 8-, 10-, 12- or 16-bit can be selected
according to the following table. The WL1 and WL0 bits in
a given DIN word control the length of the present, not the
next, DOUT word. WL1 and WL2 are never “don’t cares”
and must be set for the correct DOUT word length even
when a “dummy” DIN word is sent. On any transfer cycle,
the word length should be made equal to the number of
SCLK cycles sent by the MPU.
WL1 WL0
00
01
10
11
OUTPUT WORD LENGTH
8 Bits
10 Bits
12 Bits
16 Bits
LTC1283 • AI09
Figure 2 shows how the data output (DOUT) timing can be
controlled with word length selection and MSB/LSB-first
format selection.
3. Deglitcher
A deglitching circuit has been added to the chip select
input of the LTC1283 to minimize the effects of errors
caused by noise on that input. This circuit ignores changes
in state on the CS input that are shorter in duration than
1 ACLK cycle. After a change of state on the CS input, the
LTC1283 waits for two falling edges of the ACLK before
recognizing a valid chip select. One indication of CS low
recognition is the DOUT line becoming active (leaving the
Hi-Z state). Note that the deglitching applies to both the
rising and falling CS edges.
ACLK
CS
DOUT
HI-Z
VALID OUTPUT
LOW CS RECOGINZED INTERNALLY
ACLK
CS
DOUT
VALID OUTPUT
HI-Z
HIGH CS RECOGNIZED INTERNALLY
LTC1283 • AI10
4. CS Low During Conversion
In the normal mode of operation, CS is brought high
during the conversion time (see Figure 3). The serial port
ignores any SCLK activity while CS is high. The LTC1283
will also operate with CS low during the conversion. In this
mode, SCLK must remain low during the conversion as
shown in Figure 4. After the conversion is complete, the
DOUT line will become active with the first output bit. Then
the data transfer can begin as normal.
5. Microprocessor Interfaces
The LTC1283 can interface directly (without external hard-
ware) to most popular microprocessor (MPU) synchro-
nous serial formats (see Table 2). If an MPU without a
serial interface is used, then four of the MPU’s parallel port
lines can be programmed to form the serial link to the
LTC1283. Included here are three serial interface ex-
amples and one example showing a parallel port pro-
grammed to form the serial interface.
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LTC1283C.PDF ] | |
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