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PDF MK5027DIP Data sheet ( Hoja de datos )
| Número de pieza | MK5027DIP | |
| Descripción | SS7 SIGNALLING LINK CONTROLLER | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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MK5027
SS7 SIGNALLING
LINK CONTROLLER
CMOS
FULLY COMPATIBLE WITH BOTH 8 OR 16
BIT SYSTEMS
SYSTEM CLOCK RATE TO 10MHz. DATA
RATE UP TO 2.5Mbps FOR SS7 PROTOCOL
PROCESSING,7Mbps FOR TRANSPARENT
HDLC MODE
COMPLETE LEVEL 2 IMPLEMENTATION
COMPATIBLE WITH 1988 CCITT, AT&T,
ANSI, AND BELLCORE SIGNALLING SYS-
TEM NUMBER 7 LINK LEVEL PROTOCOLS
52 PIN PLCC AND 48-PIN DIP PIN-FOR-PIN
COMPATIBLE WITH THE SGS-THOMSON
X.25 CHIP (MK5025) AND NEARLY PIN-FOR-
PIN COMPATIBLE WITH THE SGS-THOM-
SON VLANCE CHIP (MK5032)
BUFFER MANAGEMENT INCLUDES:
- Initialization Block
- Separate Receive and Transmit Rings
- Variable Descriptor Ring and Window Sizes.
ON CHIP DMA CONTROL WITH PROGRAM-
MABLE BURST LENGTH
SELECTABLE BEC OR PCR RETRANSMIS-
SION METHODS, INCLUDING FORCED RE-
TRANSMISSION FOR PCR
HANDLES ALL 7 SS7 TIMERS
HANDLES ALL SS7 FRAME FORMATTING:
- Zero bit insert and delete
- FCS generation and detection
- Frame delimiting with flags
PROGRAMMABLE MINIMUM SIGNAL UNIT
SPACING (number of flags between SU’s)
HANDLES ALL SEQUENCING AND LINK
CONTROL
SELECTABLE FCS OF 16 OR 32 BITS.
TESTING FACILITIES:
- Internal Loopback
- Silent Loopback
- Optional Internal Data Clock Generation
- Self Test
ALL INPUTS AND OUTPUTS ARE TTL COM-
PATIBLE
PROGRAMMABLE FOR FULL OR HALF DU-
PLEX OPERATION
DESCRIPTION
The SGS-THOMSON Signalling System #7 Sig-
nalling Link Controller (MK5027) is a VLSI semi-
August 1989
DIP48
PLCC52
conductor device which provides a complete link
control function conforming to the 1988 CCITT
version of SS7. This includes frame formatting,
transparency (so called ”bit-stufling”), error recov-
ery by two types of retransmission, error monitor-
ing, sequence number control, link status con-
trol, and FISU generation. One of the outstanding
features of the MK5027 is its buffer management
which includes on-chip DMA. This feature allows
users to handlq multiple packets of receive and
transmit data at a time. (A conventional data link-
control chip plus a separate DMA chip would han-
dle data for only a single block at a time.) The
MK5027 may be used with any of several popular
16 and 8 bit microprocessors, such as 68000,
6800, Z8000, Z80, LSI-11, 8086, 8088, 8080, etc.
Figure 1: Pin Connection.
VSS-GND
DAL 07
DAL 06
DAL 05
DAL 04
DAL 03
DAL 02
DAL 01
DAL 00
READ
INTR
DALI
DALO
DAS
BMO, BYTE, BUSREL
BMI, BUSAKO
HOLD, BUSRQ
ALE, AS
HLDA
CS
ADR
READY
RESET
VSS-GND
1
2
3
4
5
6
7
8
9M
10 K
11
5
12
13 0
14 H
15
2
16
17 5
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VCC (+5V)
DAL08
DAL09
DAL10
DAL11
DAL12
DAL13
DAL14
DAL15
A16
A17
A18
A19
A20
A21
A22
A23
RD
DSR, CTS
TD
SYSCLK
RCLK
DTR, RTS
TCLK
1/19
1 page  
Figure 2: Possible System Configuration for the MK5027.
MK5027
5/19
5 Page 
MK5027
AC TIMING SPECIFICATIONS (Continued)
TA = 0 °C to 70 °C, VCC = +5V ±5 percent, unless otherwise specified.
No Signal
13 RCLK
14 RCLK
15 RCLK
16 RCLK
17 RCLK
18 RD
19 RD
20 RD
21 RD
22 A/DAL
23 A/DAL
24 HLDA
25 RESET
26 A/DAL
27 A
28 A
29 DAL
30 DAL
31 DAL
32 DAL
33 DAL
34 DAL
35 DAL
36 DAL
37 DAL
38 DAL
39 ALE
40 ALE
41 DAS
Symbol
TRCT
TRCH
TRCL
TRCR
TRCF
TRDR
TRDF
TRDH
TRDS
TDOFF
TDON
THHA
TRW
TCYCLE
TXAS
TXAH
TAS
TAH
TRDAS
TRDAH
TDDAS
TWDS
TWDH
TSRDH
TSWDH
TSWDS
TALEW
TDSW
TDSW
Parameter
RCLK period
RCLK high time
RCLK low time
Rise time of RCLK
Fall time of RCLK
RD data rise time
RD data fall time
RD hold time after rising edge of
RCLK
RD setup time prior to rising edge of
RCLK
Bus Master driver disable after rising
edge of HOLD
Bus Master driver enable after falling
edge of HLDA
Delay to falling edge of HLDA from
falling edge of HOLD (Bus Master)
RESET pulse width
Read/write, address/data Cycle Time
Address setup time to falling edge
of ALE
Address hold time after the rising
edge of DAS
Address setup time to falling edge
of ALE
Address hold time after the falling
edge of ALE
Data setup time to the falling edge
of DAS (Bus Master read)
Data hold time after the rising edge
of DAS (bus master read)
Data setup time to the falling edge of
DAS (bus master write)
Data setup time to the rising edge of
DAS (bus master write)
Data hold time to the rising edge of
DAS (bus slave write)
Data hold time after the rising edge
of DAS (bus slave read)
Data hold time after the rising edge
of DAS (bus slave write)
Data setup time to the falling edge of
DAS (bus slave write)
ALE width high
Delay from rising edge od DAS to
the rising edge of ALE
DAS width low
Test
Conditions
TSCT = 100ns
TSCT = 100ns
TSCT = 100ns
Min.
140
63
63
0
0
0
0
5
30
0
0
0
30
600
100
50
75
20
55
0
0
250
35
0
0
0
110
70
200
Typ.
Max.
8
8
8
8
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
50 ns
200 ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
35 ns
ns
ns
ns
ns
ns
11/19
11 Page | ||
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| PDF Descargar | [ Datasheet MK5027DIP.PDF ] | |
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