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PDF MCM72JG32SG66 Data sheet ( Hoja de datos )
| Número de pieza | MCM72JG32SG66 | |
| Descripción | 256KB and 512KB Pipelined BurstRAM Secondary Cache Module for Pentium | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Advance Information
256K and 512K Pipelined
BurstRAM™ Sedcondary Cache
Module for Pentium™
The MCM72JG32 and MCM72JG64 are designed to provide a burstable, high
performance, 256K/512K L2 cache for the Pentium microprocessor in conjunc-
tion with Intel’s Triton chip set. The modules are configured as 32K x 64 and
64K x 64 bits in a 160 pin card edge memory module. Each module uses four of
Motorola’s 5 V 32K x 18 or 64K x 18 BurstRAMs and one Motorola 5 V 32K x 8
FSRAM for the tag RAM.
Bursts can be initiated with either address status processor (ADSP) or cache
address status (CADS). Subsequent burst addresses are generated internal to
the BurstRAM by the cache burst advance (CADV) input pin.
Write cycles are internally self timed and are initiated by the rising edge of the
clock (CLK0, CLK1) input. Eight write enables are provided for byte write control.
PD0 – PD4 map into the Triton chip set for auto–configuration of the cache
control.
Module family pinout supports 5 V and 3.3 V components. It is recommended
that all power supplies be connected.
These cache modules are plug and pin compatible with the
MCM64AF32SG15, a 256K byte asynchronous module also designed for the
Pentium microprocessor in conjunction with Intel’s Triton chip set.
• Pentium–Style Burst Counter on Chip
• Pipelined Data Out
• 160 Pin Card Edge Module
• Address Pipeline Supported by ADSP Disabled with Ex
• All Cache Data and Tag I/Os are TTL Compatible
• Three State Outputs
• Byte Write Capability
• Fast Module Clock Rates: 66 MHz
• Fast SRAM Access Times:15 ns for Tag RAM
9 ns for Data RAMs
• Decoupling Capacitors for Each Fast Static RAM
• High Quality Multi–Layer FR4 PWB with Separate Power and Ground
Planes
• I/Os are 3.3 V Compatible on Data RAMs
• Burndy Connector, Part Number: CELP2X80SC3Z48
• Series 20 Ω Resistors for Noise Immunity
MCM72JG32
MCM72JG64
160–LEAD CARD
EDGE
CASE 1113A–01
TOP VIEW
1
42
43
80
BurstRAM is a trademark of Motorola.
Pentium is a trademark of Intel Corp.
This document contains information on a new product. Motorola reserves the right to change or discontinue this product without notice.
REV 1
5/95
M© OMoTtoOroRla,OInLc.A19F95AST SRAM
MCM72JG32•MCM72JG64
1
1 page  
PIN DESCRIPTIONS
160–Lead Card Edge Pin Locations
20, 21, 22, 23, 24, 28, 29,
101, 102, 103, 104, 106, 108, 109, 110
36, 116
11, 12, 13, 14, 92, 93, 94, 96
8
—
—
16
30
9
89
91
38, 40, 41, 42, 44, 45, 46, 47, 49, 50, 51,
53, 54, 55, 57, 58, 59, 61, 62, 63, 65, 66,
67, 69, 70, 71, 73, 74, 75, 77, 78, 79,
118, 120, 121, 122, 124, 125, 126, 127,
129, 130, 131, 133, 134, 135, 137, 138,
139, 141, 142, 143, 145, 146, 147, 149,
150, 151, 153, 154, 155, 157, 158, 159
2, 3, 4, 5, 82, 83, 84, 85
33, 34, 112, 113, 114
7, 15, 25, 39, 52, 60, 68, 76
87, 95, 105, 119, 132, 140, 148, 156
1, 10, 19, 27, 35, 37, 43, 48, 56, 64, 72,
80, 81, 90, 99, 107, 115, 117, 123, 128,
136, 144, 152, 160
6, 17, 18, 26, 31, 32, 86, 88, 97, 98, 100,
111
Symbol
A3 – A18
CLK0,
CLK1
CWE0 –
CWE7
TWE
BWE
GWE
CCS
ADSP
CADS
CADV
COE
DQ0 –
DQ63
TIO0 –
TIO7
PD0 –
PD4
VCC3
VCC5
VSS
NC
Type
Input
Input
Input
Description
Address Inputs: These inputs are registered into data RAMs and must
meet setup and hold times. The tag RAM addresses are not registered.
Clock: This signal registers the address, data in, and all control signals
except COE.
Cache Data Byte Write Enable: Active low write signal for data RAMs.
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Tag Write Enable: Active low write signal for tag RAMs.
Byte Write Enable: To be used in future modules.
Global Write Enable: To be used in future modules.
Chip Select: Active low chip enable for data RAMs.
Address Status Processor: Initiates READ, WRITE, or chip deselect
cycle (Exception–chip deselect does not occur when ADSP is asserted
and CCS is high.
Cache Address Status: Initiates READ, WRITE, or chip deselect cycle.
Cache Burst Advance: Increments address count in accordance with
interleaved count style.
Cache Output Enable: Active low asynchronous input.
Low–enables output buffers (DQ pins)
High–DQx pins are high impedance.
Synchronous Data I/O:
Drives data out of data RAMs during READ cycles.
Stores data to data RAMs during WRITE cycles.
I/O Tag RAM I/O:
Drives data out during tag compare cycles.
Stores data to tag RAM during tag WRITE cycles.
— Presence Detect: See Presence Detect Table
Supply Power Supply: 3.3 V ± 5%.
Supply Power Supply: 5.0 V ± 5%.
Supply Ground
— No Connection: There is no connection to the module.
MOTOROLA FAST SRAM
MCM72JG32•MCM72JG64
5
5 Page 
MOTOROLA FAST SRAM
MCM72JG32•MCM72JG64
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MCM72JG32SG66.PDF ] | |
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