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PDF MCM72F8DG9 Data sheet ( Hoja de datos )
| Número de pieza | MCM72F8DG9 | |
| Descripción | 2MB and 4MB Synchronous Fast Static RAM Module | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
2MB and 4MB Synchronous Fast
Static RAM Module
The MCM72F8 (2MB) is configured as 256K x 72 bits and the MCM72F9 (4MB)
is configured as 512K x 72 bits. Both are packaged in a 168–pin dual–in–line
memory module DIMM. Each module uses Motorola’s 3.3 V 256K x 18 bit
flow–through BurstRAMs.
Address (A), data inputs (DQ, DP), and all control signals except output enable
(G) are clock (K) controlled through positive–edge–triggered noninverting
registers.
Write cycles are internally self–timed and initiated by the rising edge of the
clock (K) input. This feature provides increased timing flexibility for incoming
signals. Synchronous byte write (W) allows writes to either individual bytes or to
both bytes.
• Single 3.3 V + 10%, – 5% Power Supply
• Plug and Pin Compatibility with 2MB and 4MB
• Multiple Clock Pins for Reduced Loading
• All Inputs and Outputs are LVTTL Compatible
• Byte Write Capability
• Fast SRAM Access Times: 8/9/12 ns
• Decoupling Capacitors for Each Fast Static RAM
• High Quality Multi–Layer FR4 PWB With Separate Power and Ground
Planes
• Amp Connector, Part Number: 390064–4
• 168–Pin DIMM Module
Order this document
by MCM72F8/D
MCM72F8
MCM72F9
168–LEAD DIMM
CASE 1115J–01
TOP VIEW
1
11
40
41
84
REV 3
11/26/97
M© OMoTtoOroRla,OInLc.A19F97AST SRAM
MCM72F8•MCM72F9
1
1 page  
PIN DESCRIPTIONS
Pin Locations
61, 62, 64, 65, 67, 68, 70, 71,
72, 143, 145, 146, 148, 149,
151, 152, 154, 155
156
Symbol
A0 – A17
ADSP
15, 31, 44, 86, 92, 105, 121,
134
2, 3, 5, 6, 8, 9, 11, 12, 14, 17,
18, 20, 21, 23, 24, 26, 27, 32,
34, 35, 37, 38, 40, 41, 43, 46,
47, 49, 50, 52, 53, 55, 56, 87,
89, 90, 93, 95, 96, 98, 99,
101, 102, 104, 107, 108, 110,
111, 115, 116, 118, 119, 122,
124, 125, 127, 128, 130, 131,
133, 136, 137, 139, 140
167, 83
DP0 – DP7
DQ0 – DQ63
E0, E1
166, 82
G0, G1
29, 74, 113, 158
K0 – K3
76, 77, 79, 80,
160, 161, 163, 164
4, 16, 33, 45, 57, 69, 94,
106, 123, 135, 147, 165
1, 7, 10, 13, 19, 22, 25, 28,
30, 36, 39, 42, 48, 51, 54, 60,
63, 66, 73, 75, 78, 81, 84, 85,
88, 91, 97, 100, 103, 109,
112, 114, 117, 120, 126, 129,
132, 138, 141, 144, 150, 153,
157, 159, 162, 168
58, 59, 142
W0 – W7
VDD
VSS
NC
Type
Input
Description
Synchronous Address Inputs: These inputs are registered and must meet
setup and hold times.
Input
Synchronous Addresss Status Controller: Initiates read, write, or chip
deselect cycle.
Synchronous Parity Data Inputs/Outputs.
I/O Synchronous Data Inputs/Outputs.
Input
Input
Input
Input
Supply
Synchronous Chip Enable: Active low to enable chip. Negated high —
blocks ADSP or deselects chip when ADSC is asserted. E1 is only used on
4MB module.
Asynchronous Output Enable Input:
Low — enables output buffer.
High — DQx pins are high impedance.
G1 is only used on 4MB module.
Clock: This signal registers the address, data in, and all control signals
except G and LBO.
Synchronous Byte Write Inputs: x refers to the byte being written (byte a,
b). SGW overrides SBx.
Power Supply: 3.3 V + 10%, – 5%. Must be connected on all modules.
Supply Ground.
No Connection: There is no connection to the chip.
DATA RAM MCM69F618A SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, 3, and 4)
Next Cycle
Address Used
E ADSP G
DQx
WRITE
Deselect
None
1 0 X High–Z X
Begin Read
External Address
000
DQ Read
Read
Current
X
1
1
High–Z
Read
Read
Current
X10
DQ Read
Begin Write
External
0 0 X High–Z Write
Write
Current
X 1 X High–Z Write
NOTES:
1. X = don’t care, 1 = logic high, 0 = logic low.
2. Write is defined as any Wx low.
3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.
4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must
also remain negated at the completion of the write cycle to ensure proper write data hold times.
MOTOROLA FAST SRAM
MCM72F8•MCM72F9
5
5 Page 
PACKAGE DIMENSIONS
168–LEAD DIMM
CASE 1115J–01
D1
0.15 (0.006) M A B C
A ÉÉÉ1ÉÉÉÉD5ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉCÉÉÉOMAPÉRÉÉÉCOLENAEÉNÉÉÉT (ÉDÉÉÉATUÉÉÉÉMPLÉAÉÉÉNECÉÉÉÉ) ÉÉÉÉÉÉÉÉ84ÉÉÉ
10 11 VIEW C
40 41
D6
VIEW B
A D4 D4
D3
D2 /2
VIEW C
VIEW D
D2
E
A1
NOTE 4
E2
NOTE 5
E1 NOTE 6
0.016 (0.4) M
B
FRONT VIEW
ÉÉÉ8ÉÉÉÉ5 ÉÉÉÉ94 ÉÉÉÉ95 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉCOMAPÉRÉÉÉOENAEÉÉÉÉNT ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ168 ÉÉÉ
SIDE VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
BACK VIEW
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCH.
3. CARD THICKNESS APPLIES ACROSS TABS AND
INCLUDES PLATING AND/OR METALLIZATION.
R
A5
ÉÉÉÉK ÉÉÉÉ
ÉÉÉÉR ÉÉÉÉ A5
C
4. DIMENSIONS E AND A1 DEFINE A
DOUBLE–SIDED MODULE.
5. DIMENSION E2 DEFINES OPTIONAL
SINGLE–SIDED MODULE
6. STRAIGHTNESS CALLOUT APPLIES TO TAB
AREA ONLY.
7. D5 DIMENSION DEFINES SLOT END AND EDGE
OF COMPONENT AREA.
0.004 (0.1) M A B C
K
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
VIEW A
0.004 (0.1) M A B C
A 1.095 1.105 27.81 28.07
A1 0.390 ––– 9.90 –––
VIEW B
A2 0.118 BSC
A3 0.700 BSC
3.00 BSC
17.78 BSC
A4 0.154 0.161 3.90 4.10
168X b
ÉÉÉÉ0.004 (0.1) M A B C
ÉÉÉÉ168X L1
ÉÉÉ ÉÉÉÉÉÉÉÉ1 168X L
ÉÉÉ ÉÉÉÉÉÉÉÉVIEWD
162X e
R
84
2X A4
0.004 (0.1) M A B C
2X A3
2X A2
A5 0.118 0.128 3.00 3.25
b 0.037 0.041 0.95 1.05
D1 5.245 5.255 133.22 133.48
D2 5.014 BSC
127.35 BSC
D3 1.700 BSC
43.18 BSC
D4 0.250 BSC
6.35 BSC
D5 0.118 ––– 3.00 –––
D6 0.125 BSC
3.175 BSC
e 0.050 BSC
1.27 BSC
E ––– 0.200 ––– 4.00
E1 0.046 0.054 1.17 1.37
E2 ––– 0.148 ––– 2.70
K 0.075 0.083 1.90 2.10
L 0.100 ––– 2.54 –––
L1 ––– 0.010 ––– 0.25
P 0.114 0.122 2.90 3.10
2X P
VIEW C
0.004 (0.1) M A B C
MOTOROLA FAST SRAM
MCM72F8•MCM72F9
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MCM72F8DG9.PDF ] | |
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