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PDF MCM72F7DG12 Data sheet ( Hoja de datos )

Número de pieza MCM72F7DG12
Descripción 512KB and 1MB Synchronous Fast Static RAM Module
Fabricantes Motorola Semiconductors 
Logotipo Motorola Semiconductors Logotipo



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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
512KB and 1MB Synchronous
Fast Static RAM Module
The MCM72F6 (512KB) is configured as 64K x 72 bits and the MCM72F7
(1MB) is configured as 128K x 72 bits. Both are packaged in a 168–pin dual–
in–line memory module DIMM. Each module uses Motorola’s 3.3 V 64K x 18 bit
flow–through BurstRAMs.
Address (A), data inputs (DQ, DP), and all control signals except output enable
(G) are clock (K) controlled through positive–edge–triggered noninverting reg-
isters.
Write cycles are internally self–timed and initiated by the rising edge of the
clock (K) input. This feature provides increased timing flexibility for incoming
signals. Synchronous byte write (W) allows writes to either individual bytes or to
both bytes.
Single 3.3 V + 10%, – 5% Power Supply
Plug and Pin Compatibility with 2MB and 4MB
Multiple Clock Pins for Reduced Loading
All Inputs and Outputs are LVTTL Compatible
Byte Write Capability
Fast SRAM Access Times: 9/10/12 ns
Decoupling Capacitors for Each Fast Static RAM
High Quality Multi–Layer FR4 PWB With Separate Power and Ground
Planes
Amp Connector, Part Number: 390064–4
168–Pin DIMM Module
Order this document
by MCM72F6/D
MCM72F6
MCM72F7
168–LEAD DIMM
CASE 1115J–01
TOP VIEW
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M© OMoTtoOroRla,OInLc.A19F97AST SRAM
MCM72F6MCM72F7
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MCM72F7DG12 pdf
PIN DESCRIPTIONS
Pin Locations
62, 64, 65, 67, 68, 70, 71,
72, 145, 146, 148, 149,
151, 152, 154, 155
156
Symbol
A0 – A15
ADSP
15, 31, 44, 86, 92, 105, 121,
134
2, 3, 5, 6, 8, 9, 11, 12, 14, 17,
18, 20, 21, 23, 24, 26, 27, 32,
34, 35, 37, 38, 40, 41, 43, 46,
47, 49, 50, 52, 53, 55, 56, 87,
89, 90, 93, 95, 96, 98, 99,
101, 102, 104, 107, 108, 110,
111, 115, 116, 118, 119, 122,
124, 125, 127, 128, 130, 131,
133, 136, 137, 139, 140
167, 83
DP0 – DP7
DQ0 – DQ63
E0, E1
166, 82
G0, G1
29, 74, 113, 158
K0 – K3
76, 77, 79, 80,
160, 161, 163, 164
4, 16, 33, 45, 57, 69, 94,
106, 123, 135, 147, 165
1, 7, 10, 13, 19, 22, 25, 28,
30, 36, 39, 42, 48, 51, 54, 60,
63, 66, 73, 75, 78, 81, 84, 85,
88, 91, 97, 100, 103, 109,
112, 114, 117, 120, 126, 129,
132, 138, 141, 144, 150, 153,
157, 159, 162, 168
58, 59, 61, 142, 143
W0 – W7
VDD
VSS
NC
Type
Input
Description
Synchronous Address Inputs: These inputs are registered and must meet
setup and hold times.
Input
Synchronous Addresss Status Controller: Initiates read, write, or chip
deselect cycle.
Synchronous Parity Data Inputs/Outputs.
I/O Synchronous Data Inputs/Outputs.
Input
Input
Input
Input
Supply
Synchronous Chip Enable: Active low to enable chip. Negated high —
blocks ADSP or deselects chip when ADSC is asserted. E1 is only used on
1MB module.
Asynchronous Output Enable Input:
Low — enables output buffer.
High — DQx pins are high impedance.
G1 is only used on 1MB module.
Clock: This signal registers the address, data in, and all control signals
except G and LBO.
Synchronous Byte Write Inputs: x refers to the byte being written (byte a,
b). SGW overrides SBx.
Power Supply: 3.3 V + 10%, – 5%. Must be connected on all modules.
Supply Ground.
No Connection: There is no connection to the chip.
DATA RAM MCM69F618A SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, 3 and 4)
Next Cycle
Address Used
E ADSP G
DQx
WRITE
Deselect
None
1 0 X High–Z X
Begin Read
External Address
000
DQ Read
Read
Current
X
1
1
High–Z
Read
Read
Current
X10
DQ Read
Begin Write
External
0 0 X High–Z Write
Write
Current
X 1 X High–Z Write
NOTES:
1. X = don’t care, 1 = logic high, 0 = logic low.
2. Write is defined as any Wx low.
3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.
4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must
also remain negated at the completion of the write cycle to ensure proper write data hold times.
MOTOROLA FAST SRAM
MCM72F6MCM72F7
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