|
|
PDF MCM69P819 Data sheet ( Hoja de datos )
| Número de pieza | MCM69P819 | |
| Descripción | 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MCM69P819 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
|
No Preview Available !
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
256K x 18 Bit Pipelined
BurstRAM Synchronous
Fast Static RAM
The MCM69P819 is a 4M bit synchronous fast static RAM designed to provide
a burstable, high performance, secondary cache for the PowerPC™ and other
high performance microprocessors. It is organized as 256K words of 18 bits
each. This device integrates input registers, an output register, a 2–bit address
counter, and high speed SRAM onto a single monolithic circuit for reduced parts
count in cache data RAM applications. Synchronous design allows precise cycle
control with the use of an external clock (K).
Addresses (SA), data inputs (DQx), and all control signals except output
enable (G) and linear burst order (LBO) are clock (K) controlled through positive–
edge–triggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
addresses can be generated internally by the MCM69P819 (burst sequence
operates in linear or interleaved mode dependent upon the state of LBO) and
controlled by the burst address advance (ADV) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-
nous write enable (SW) are provided to allow writes to either individual bytes or
to all bytes. The two bytes are designated as “a” and “b”. SBa controls DQa and
SBb controls DQb. Individual bytes are written if the selected byte writes SBx are
asserted with SW. All bytes are written if either SGW is asserted or if all SBx and
SW are asserted.
For read cycles, pipelined SRAMs output data is temporarily stored by an
edge–triggered output register and then released to the output buffers at the next
rising edge of clock (K).
The MCM69P819 operates from a 3.3 V core power supply and all outputs
operate on a 2.5 or 3.3 V power supply. All inputs and outputs are JEDEC stan-
dard JESD8–5 compatible.
• MCM69P819–3.5: 3.5 ns Access/6 ns Cycle (166 MHz)
MCM69P819–3.8: 3.8 ns Access/6.7 ns Cycle (150 MHz)
MCM69P819–4: 4 ns Access/7.5 ns Cycle (133 MHz)
• 3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Single–Cycle Deselect Timing
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• PB1 Version 2.0 Compatible
• JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages
Order this document
by MCM69P819/D
MCM69P819
ZP PACKAGE
PBGA
CASE 999–02
TQ PACKAGE
TQFP
CASE 983A–01
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
REV 6
1/20/98
M© OMoTtoOroRla,OInLc.A19F98AST SRAM
MCM69P819
1
1 page  
TQFP PIN DESCRIPTIONS
Pin Locations
85
84
83
(a) 58, 59, 62, 63, 68, 69, 72, 73, 74
(b) 8, 9, 12, 13, 18, 19, 22, 23, 24
86
89
31
32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50,
80, 81, 82, 99, 100
36, 37
93, 94
(a) (b)
98
97
92
88
87
15, 41, 65, 91
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 17, 21, 26, 40,
55, 60, 67, 71, 76, 90
1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, 38,
39, 42, 43, 51, 52, 53, 56, 57, 64, 66, 75,
78, 79, 95, 96
Symbol
ADSC
ADSP
ADV
DQx
G
K
LBO
SA
SA1, SA0
SBx
SE1
SE2
SE3
SGW
SW
VDD
VDDQ
VSS
NC
Type
Description
Input
Synchronous Address Status Controller: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
READ, WRITE, or chip deselect.
Input
Synchronous Address Status Processor: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
new READ, WRITE, or chip deselect (exception — chip deselect does
not occur when ADSP is asserted and SE1 is high).
Input Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
I/O Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b).
Input
Asynchronous Output Enable Input:
Low — enables output buffers (DQx pins).
High — DQx pins are high impedance.
Input Clock: This signal registers the address, data in, and all control signals
except G and LBO.
Input
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).
Input Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
Input
Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte
a, b). SGW overrides SBx.
Input
Synchronous Chip Enable: Active low to enable chip.
Negated high — blocks ADSP or deselects chip when ADSC is
asserted.
Input Synchronous Chip Enable: Active high for depth expansion.
Input Synchronous Chip Enable: Active low for depth expansion.
Input
Synchronous Global Write: This signal writes all bytes regardless of the
status of the SBx and SW signals. If only byte write signals SBx are
being used, tie this pin high.
Input
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins. If only byte write signals SBx
are being used, tie this pin low.
Supply Core Power Supply.
Supply I/O Power Supply.
Supply Ground.
— No Connection: There is no connection to the chip.
MOTOROLA FAST SRAM
MCM69P819
5
5 Page 
5
4
OUTPUT
3
CL
2
1
0
0 20 40 60 80 100
LUMPED CAPACITANCE, CL (pF)
Figure 3. Lumped Capacitive Load and Typical Derating Curve
OUTPUT LOAD
OUTPUT
BUFFER
TEST POINT
INPUT
WAVEFORM
UNLOADED RISE AND FALL TIME MEASUREMENT
2.0
0.5
2.0
0.5
OUTPUT
WAVEFORM
2.0
0.5
tr
NOTES:
1. Input waveform has a slew rate of 1 V/ns.
2. Rise time is measured from 0.5 to 2.0 V unloaded.
3. Fall time is measured from 2.0 to 0.5 V unloaded.
2.0
0.5
tf
Figure 4. Unloaded Rise and Fall Time Characterization
MOTOROLA FAST SRAM
MCM69P819
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MCM69P819.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MCM69P817 | 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM | Motorola Semiconductors |
| MCM69P818 | 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM | Motorola Semiconductors |
| MCM69P819 | 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM | Motorola Semiconductors |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |