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PDF MCM69L819AZP9.5R Data sheet ( Hoja de datos )
| Número de pieza | MCM69L819AZP9.5R | |
| Descripción | 4M Late Write LVTTL | |
| Fabricantes | Motorola Semiconductors | |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
4M Late Write LVTTL
The MCM69L737A/819A is a 4 megabit synchronous late write fast static RAM
designed to provide high performance in secondary cache and ATM switch,
Telecom, and other high speed memory applications. The MCM69L819A
organized as 256K words by 18 bits, and the MCM69L737A organized as 128K
words by 36 bits wide are fabricated in Motorola’s high performance silicon gate
BiCMOS technology.
The differential CK clock inputs control the timing of read/write operations of
the RAM. At the rising edge of the CK clock all addresses, write enables, and
synchronous selects are registered. An internal buffer and special logic enable
the memory to accept write data on the rising edge of the CK clock a cycle after
address and control signals. Read data is available at the falling edge of the CK
clock.
The RAM uses LVTTL 3.3 V inputs and outputs.
The synchronous write and byte enables allow writing to individual bytes or the
entire word.
• Byte Write Control
• Single 3.3 V + 10%, – 5% Operation
• LVTTL 3.3 V I/O (VDDQ)
• Register to Latch Synchronous Operation
• Asynchronous Output Enable
• Boundary Scan (JTAG) IEEE 1149.1 Compatible
• Differential Clock Inputs
• Optional x18 or x36 organization
• MCM69L737A/819A–8.5 = 8.5 ns
MCM69L737A/819A–9 = 9 ns
MCM69L737A/819A–9.5 = 9.5 ns
• Sleep Mode Operation (ZZ Pin)
• 119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array
(PBGA) Package
Order this document
by MCM69L737A/D
MCM69L737A
MCM69L819A
ZP PACKAGE
PBGA
CASE 999–01
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 1
8/15/97
M© OMoTtoOroRla,OInLc.A19F9A7 ST SRAM
MCM69L737A•MCM69L819A
1
1 page  
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS, See Note 1)
Rating
Symbol
Value
Unit
Core Supply Voltage
VDD
– 0.5 to + 4.6
V
Output Supply Voltage
VDDQ – 0.5 to VDD + 0.5 V
Voltage On Any Pin
Vin – 0.5 to VDD + 0.5 V
Input Current (per I/O)
Iin ± 50 mA
Output Current (per I/O)
Iout ± 70 mA
Power Dissipation (See Note 2)
PD — W
Operating Temperature
TA
0 to + 70
°C
Temperature Under Bias
Tbias
– 10 to + 85
°C
Storage Temperature
Tstg
– 55 to + 125
°C
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
2. Power dissipation capability will be dependent upon package characteristics and use
environment. See enclosed thermal impedance data.
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will ensure
the output devices are in High–Z at power up.
PBGA PACKAGE THERMAL CHARACTERISTICS
Rating
Symbol
Max Unit Notes
Junction to Ambient (Still Air)
RθJA
53
°C/W
1, 2
Junction to Ambient (@200 ft/min)
Single Layer Board
RθJA
38
°C/W
1, 2
Junction to Ambient (@200 ft/min)
Four Layer Board
RθJA
22 °C/W
Junction to Board (Bottom)
RθJB
14
°C/W
3
Junction to Case (Top)
RθJC
5
°C/W
4
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC–883
Method 1012.1).
CLOCK TRUTH TABLE
K CLK
ZZ
SS
L–H
L
L
L–H
L
L
L–H
L
L
L–H
L
L
L–H
L
L
L–H
L
L
L–H
L
L
L–H
L
H
XHX
SW SBa SBb SBc SBd DQ (n) DQ (n+1)
Mode
HX
X
X
X Dout 0–35
X
Read Cycle All Bytes
L
L
H
H
H
High–Z
Din 0–8
Write Cycle 1st Byte
L
H
L
H
H
High–Z Din 9–17
Write Cycle 2nd Byte
L
H
H
L
H
High–Z Din 18–26
Write Cycle 3rd Byte
L
H
H
H
L
High–Z Din 27–35
Write Cycle 4th Byte
L
L
L
L
L
High–Z Din 0–35
Write Cycle All Bytes
L
H
H
H
H
High–Z
High–Z
Abort Write Cycle
X X X X X High–Z X
Deselect Cycle
X
X
X
X
X
High–Z
High–Z
Sleep Mode
MOTOROLA FAST SRAM
MCM69L737A•MCM69L819A
5
5 Page 
FUNCTIONAL OPERATION
READ AND WRITE OPERATIONS
All control signals except G are registered on the rising
edge of the CK clock. These signals must meet the setup
and hold times shown in the AC Characteristics table. On the
falling edge of the current cycle, the output latch becomes
transparent and data is available. The output data is latched
on the rising edge of the next clock. The output data is avail-
able at the output at tKLQV or tKHQV whichever is later.
tKHQV is the internal latency of the device. During this same
cycle a new read address can be applied to the address pins.
A write cycle can occur on the next cycle as long as tKHQZ
and tDVKH are met. Read cycles may follow write cycles im-
mediately.
G, SS, and SW control output drive. Chip deselect via a
high on SS at the rising edge of the CK clock has its effect on
the output drivers immediately. SW low deselects the output
drivers immediately (on the same cycle). Output selecting via
a low on SS and high on SW at a rising CK clock has its ef-
fect on the output drivers at tKLQX. Output drive is also con-
trolled directly by output enable, G. G is an asynchronous
input. No clock edges are required to enable or disable the
output with G.
Output data will be valid the latter of tGLQV, tKHQV, or
tKLQV. Outputs will begin driving at tKLQX1. Outputs will
hold previous data until tKLQX, tGHQX or tKHQZ in the case of
a write following a read.
WRITE AND BYTE WRITE FUNCTIONS
Note that in the following discussion the term “byte” refers
to nine bits of the RAM I/O bus. In all cases, the timing pa-
rameters described for synchronous write input (SW) apply
to each of the byte write enable inputs (SBa, SBb, etc.).
Byte write enable inputs have no effect on read cycles.
This allows the system designer not interested in performing
byte writes to connect the byte enable inputs to active low
(VSS). Reads of all bytes proceed normally and write cycles,
activated via a low on SW, and the rising edge of the CK
clock, write the entire RAM I/O width. This way the designer
is spared having to drive multiple write input buffer loads.
Byte writes are performed using the byte write enable in-
puts in conjunction with the synchronous write input (SW). It
is important to note that writing any one byte will inhibit a read
of all bytes at the current address. The RAM cannot simulta-
neously read one byte and write another at the same ad-
dress. A write cycle initiated with none of the byte write
enable inputs active is neither a read or a write. No write will
occur, but the outputs will be deselected as in a normal write
cycle.
LATE WRITE
The write address is sampled on the first rising edge of
clock and write data is sampled on the following rising edge.
The late write feature is implemented with single stage
write buffering. Write buffering is transparent to the user. A
comparator monitors the address bus and, when necessary,
routes buffer contents to the outputs to assure coherent op-
eration. This occurs in all cases whether there is a byte write
or a full word is written.
POWER UP AND INITIALIZATION
The following supply voltage application sequence is
recommended: VSS, VDD, then VDDQ. Please note, per the
Absolute Maximum Ratings table, VDDQ is not to exceed VDD
+ 0.5 V, whatever the instantaneous value of VDD. Once
supplies have reached specification levels, a minimum dwell
of 1.0 ms with C/K clock inputs cycling is required before
beginning normal operations.
MOTOROLA FAST SRAM
MCM69L737A•MCM69L819A
11
11 Page | ||
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| PDF Descargar | [ Datasheet MCM69L819AZP9.5R.PDF ] | |
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