|
|
PDF MCM63F733A Data sheet ( Hoja de datos )
| Número de pieza | MCM63F733A | |
| Descripción | 128K x 32 Bit Flow-Through BurstRAM Synchronous Fast Static RAM | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MCM63F733A (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
128K x 32 Bit Flow–Through
BurstRAM Synchronous
Fast Static RAM
The MCM63F733A is a 4M–bit synchronous fast static RAM designed to pro-
vide a burstable, high performance, secondary cache for the PowerPC™ and
other high performance microprocessors. It is organized as 128K words of 32
bits each, fabricated with high performance silicon gate CMOS technology.
This device integrates input registers, a 2–bit address counter, and high speed
SRAM onto a single monolithic circuit for reduced parts count in cache data
RAM applications. Synchronous design allows precise cycle control with the
use of an external clock (K). CMOS circuitry reduces the overall power con-
sumption of the integrated functions for greater reliability.
Addresses (SA), data inputs (DQx), and all control signals except output
enable (G) and Linear Burst Order (LBO) are clock (K) controlled through
positive–edge–triggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
addresses can be generated internally by the MCM63F733A (burst sequence
operates in linear or interleaved mode dependent upon state of LBO) and con-
trolled by the burst address advance (ADV) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-
nous write enable (SW) are provided to allow writes to either individual bytes or
to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls
DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte
writes SBx are asserted with SW. All bytes are written if either SGW is asserted
or if all SBx and SW are asserted.
For read cycles, a flow–through SRAM allows output data to simply flow freely
from the memory array.
The MCM63F733A operates from a 3.3 V core power supply and all outputs
operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC
Standard JESD8–5 compatible.
• MCM63F733A–10 = 10 ns Access/13 ns Cycle (75 MHz)
MCM63F733A–11 = 11 ns Access/15 ns Cycle (66 MHz)
• 3.3 V + 10% / – 5% Core, Power Supply, 2.5 V or 3.3 V I/O Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• Single–Cycle Deselect
• Sleep Mode (ZZ)
• 100–Pin TQFP Package
Order this document
by MCM63F733A/D
MCM63F733A
TQ PACKAGE
TQFP
CASE 983A–01
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 2
3/20/98
©MMOoTtoOrolRa,OIncL.A19F98AST SRAM
MCM63F733A
1
1 page  
TRUTH TABLE (See Notes 1 through 5)
Next Cycle
Address
Used
SE1 SE2 SE3 ADSP ADSC ADV G 3
DQx
Write 2, 4
Deselect
None 1 X X X 0 X X High–Z
X
Deselect
None
0X1 0
X X X High–Z
X
Deselect
None
00X 0
X X X High–Z
X
Deselect
None
XX1 1
0 X X High–Z
X
Deselect
None
X0X 1
0 X X High–Z
X
Begin Read
External
0
1
0
0
X X X High–Z
X
Begin Read
External
0
1
0
1
0 X X High–Z READ
Continue Read
Next
XXX
1
1
0 1 High–Z READ
Continue Read
Next
XXX
1
1
0 0 DQ
READ
Continue Read
Next
1XX X
1 0 1 High–Z READ
Continue Read
Next
1XX X
1 0 0 DQ
READ
Suspend Read
Current X X X
1
1
1 1 High–Z READ
Suspend Read
Current X X X
1
1
1 0 DQ
READ
Suspend Read
Current 1 X X X 1 1 1 High–Z READ
Suspend Read
Current 1 X X X 1 1 0 DQ
READ
Begin Write
External
0
1
0
1
0 X X High–Z WRITE
Continue Write
Next
XXX
1
1
0 X High–Z WRITE
Continue Write
Next
1XX X
1 0 X High–Z WRITE
Suspend Write
Current X X X
1
1
1 X High–Z WRITE
Suspend Write
Current 1 X X X 1 1 X High–Z WRITE
NOTES:
1. X = Don’t Care. 1 = logic high. 0 = logic low.
2. Write is defined as either 1) any SBx and SW low, or 2) SGW is low.
3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.
4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times.
G must also remain negated at the completion of the write cycle to ensure proper write data hold times.
ASYNCHRONOUS TRUTH TABLE
Operation
Read
Read
Write
Deselected
Selected
ZZ
L
L
L
L
H
G I/O Status
L Data Out (DQx)
H High–Z
X High–Z
X High–Z
X High–Z
LINEAR BURST ADDRESS TABLE (LBO = VSS)
1st Address (External)
2nd Address (Internal)
X . . . X00
X . . . X01
X . . . X01
X . . . X10
X . . . X10
X . . . X11
X . . . X11
X . . . X00
3rd Address (Internal)
X . . . X10
X . . . X11
X . . . X00
X . . . X01
4th Address (Internal)
X . . . X11
X . . . X00
X . . . X01
X . . . X10
MOTOROLA FAST SRAM
MCM63F733A
5
5 Page 
VOLTAGE (V)
– 0.5
0
0.8
1.25
1.5
2.3
2.7
2.9
PULL–UP
I (mA) MIN
– 38
– 38
– 38
– 30
– 27
0
0
0
I (mA) MAX
– 105
– 105
– 105
– 83
– 75
– 40
– 15
0
2.9
2.5
2.3
1.25
0.8
0
0
(a) Pull–Up for VDDQ = 2.5 V
3.6
– 40
CURRENT (mA)
– 105
VOLTAGE (V)
– 0.5
0
1.4
1.65
2.0
3.135
3.6
PULL–UP
I (mA) MIN
– 40
– 40
– 40
– 37
– 28
0
0
I (mA) MAX
– 120
– 120
– 120
– 108
– 81
– 20
0
3.135
2.8
1.65
1.4
0
0
(b) Pull–Up: VDDQ = 3.3 V
– 40 – 80
CURRENT (mA)
– 120
VOLTAGE (V)
– 0.5
0
0.4
0.8
1.25
1.6
2.8
3.2
3.4
PULL–DOWN
I (mA) MIN
0
0
10
20
31
40
40
40
40
I (mA) MAX
0
0
20
40
63
80
80
80
80
VDD
1.6
1.25
0.3
0
0
(c) Pull–Down
40
CURRENT (mA)
Figure 4. Typical Output Buffer Characteristics
80
MOTOROLA FAST SRAM
MCM63F733A
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MCM63F733A.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MCM63F733A | 128K x 32 Bit Flow-Through BurstRAM Synchronous Fast Static RAM | Motorola Semiconductors |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |