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PDF MCM44G64 Data sheet ( Hoja de datos )
| Número de pieza | MCM44G64 | |
| Descripción | 1MB R4000 Secondary Cache Fast Static RAM Module Set | |
| Fabricantes | Motorola Semiconductors | |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM4464/D
1MB R4000 Secondary Cache
Fast Static RAM Module Set
Four MCM4464 modules comprise a full 1 MB of secondary cache for the
R4000 processor. Each module contains nine MCM6709J fast static RAMs for
a cache data size of 64K x 36. The tag portion, dependent on word line size,
contains either two MCM6709J or one MCM6706J fast static RAMs. All input sig-
nals, except A0 and WE are buffered using 74FBT2827 drivers with series 25 Ω
resistors.
The MCM6709J and MCM6706J are fabricated using high–performance sili-
con–gate BiCMOS technology. Static design eliminates the need for internal
clocks or timing strobes.
All 1MB R4000 supported secondary cache options are available.
• Single 5 V ± 10% Power Supply
• All Inputs and Outputs are TTL Compatible
• Three State Outputs
• Fast Module Access Time: 12/15/17 ns
• Zero Wait–State Operation
• Unified or Split Seconday Cache Modules are Available (See Ordering
Information for Details)
• Word Line Sizes of 4, 8, 16, and 32 are Available (See Ordering
Information for Details)
• The Pin Compatible MCM44256 Series is also Available to Support a Full
4MB R4000 Secondary Cache.
• Decoupling Capacitors are Used for Each Fast Static RAM and Buffer,
Along with Bulk Capacitance for Maximum Noise Immunity
• High Quality Multi–Layer FR4 PWB with Separate Power and Ground
Planes
PIN NAMES
A0 – A15 . . . . . . . . . . . . . . . . Address Inputs
WE . . . . . . . . . . . . . . . . . . . . . . . Write Enable
DCS . . . . . . . . . . . . . . . . . . . . . . Data Enable
TCS . . . . . . . . . . . . . . . . . . . . . . . Tag Enable
OE . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ35 . . . . . . . . . Data Input / Output
TDQ0 – TDQ7 . . . TAG Data Input / Output
VCC . . . . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
For proper operation of the device, VSS must
be connected to ground.
REV 1
8/94
MCM4464 Series
PIN ASSIGNMENT
80 LEAD SIMM — TOP VIEW
VCC 2
DQ1 4
DQ3 6
1 VSS
3 DQ0
5 DQ2
DQ5 8
VSS 10
DQ8 12
7 DQ4
9 DQ6
11 DQ7
DQ10 14
13 DQ9
DQ12
DQ14
DQ15
16
18
20
15 DQ11
17 DQ13
19 VSS
DQ17 22
DQ19 24
21 DQ16
23 DQ18
DQ21
VSS
DQ23
26
28
30
25 DQ20
27 DQ22
29 VCC
DQ25
DQ27
DQ29
DQ30
DQ32
32
34
36
38
40
31 DQ24
33 DQ26
35 DQ28
37 VSS
39 DQ31
DQ34
VSS
A0
A2
A4
42
44
46
48
50
41 DQ33
43 DQ35
45 WE
47 A1
49 A3
A6
VCC
OE
A8
A10
VSS
A13
A15
NC
TDQ0
TDQ1
TDQ3
TDQ5
TDQ7
VSS
52
54
56
58
60
62
64
66*
68*
70
72
74
76
78
80
51 A5
53 VSS
55 DCS
57 A7
59 A9
61 A11
63 A12
65 A14
67 NC
69 TCS
71 VSS
73 TDQ2
75 TDQ4
77 TDQ6
79 VCC
NOTE: Pin assignment is for unified cache. For
split cache option, Pin 68 becomes
Address MSB (A15) and Pin 66 is NC.
M© OMoTtoOroRla,OInLc.A19F94AST SRAM
MCM4464 SERIES
1
1 page  
READ CYCLE 1 (See Note)
A1 – A15
A0
Q (DATA OUT)
tA0XQX
tAXQX
PREVIOUS DATA VALID
tAVQV
tA0VQV
NOTE: Module is continuously selected (DCS or TCS = VIL, OE = VIL).
READ CYCLE 2 (See Note)
A1 – A15
A0
DCS/TCS
(DATA/TAG ENABLE)
OE (OUTPUT ENABLE)
Q (DATA OUT)
tAVQV
tA0VQV
tELQV
tELQX
tGLQX
tGLQV
NOTE: Address valid prior to or coincident with DCS or TCS going low.
DATA VALID
tEHQZ
tGHQZ
DATA VALID
MOTOROLA FAST SRAM
MCM4464 SERIES
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MCM44G64.PDF ] | |
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