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PDF MAX521 Data sheet ( Hoja de datos )
| Número de pieza | MAX521 | |
| Descripción | Quad/Octal / 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-0378; Rev 3; 9/96
Quad/Octal, 2-Wire Serial 8-Bit DACs
with Rail-to-Rail Outputs
_______________General Description
The MAX520/MAX521 are quad/octal, 8-bit voltage-output
digital-to-analog converters (DACs) with simple 2-wire ser-
ial interfaces that allow communication between multiple
devices. They operate from a single +5V supply and their
reference input range includes both supply rails.
The MAX521 includes rail-to-rail output buffer amplifiers for
reduced system size and component count when driving
loads. The MAX520’s unbuffered voltage outputs reduce
the device’s total supply current to 4µA and provide
increased accuracy at low output currents.
The MAX520/MAX521 feature a serial interface and internal
software protocol, allowing communication at data rates up
to 400kbps. The interface, combined with the double-
buffered input configuration, allows the DAC registers to be
updated individually or simultaneously. In addition, the
devices can be put into a low-power shutdown mode that
reduces supply current to 4µA. Power-on reset ensures the
DAC outputs are at 0V when power is initially applied.
The MAX520 is available in 16-pin DIP and wide SO pack-
ages, as well as a space-saving 20-pin SSOP. The
MAX521 comes in 20-pin DIP and 24-pin SO packages, as
well as a space-saving 24-pin SSOP.
________________________Applications
Minimum Component Analog Systems
Digital Offset/Gain Adjustment
Industrial Process Control
Automatic Test Equipment
Programmable Attenuators
_________________Pin Configurations
TOP VIEW
OUT1 1
OUT0 2
REF1 3
REF0 4
AGND 5
DGND 6
SCL 7
SDA 8
MAX520
16 OUT2
15 OUT3
14 REF2
13 REF3
12 VDD
11 AD2
10 AD1
9 AD0
DIP/SO
Pin Configurations continued at end of data sheet.
____________________________Features
o Single +5V Supply
o Simple 2-Wire Serial Interface
o I2C Compatible
o Outputs Swing Rail to Rail:
Unbuffered Outputs (MAX520)
Buffered Outputs (MAX521)
o 1%-Accurate Trimmed Output Resistance (MAX520A)
o Ultra-Low 4µA Supply Current (MAX520)
o Individual DACs Have Separate Reference Inputs
o Power-On Reset Clears All Latches
o 4µA Power-Down Mode
______________Ordering Information
PART†
MAX520ACPE
MAX520BCPE
MAX520ACWE
MAX520BCWE
TEMP. RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
16 Plastic DIP
16 Plastic DIP
16 Wide SO
16 Wide SO
TUE
(LSB)
1
1
1
1
Ordering Information continued at end of data sheet.
†MAX520 “A” grade parts include a 1%-accurate, factory-trimmed
output resistance.
_______________Functional Diagrams
SDA SCL
MAX520
8-BIT 8
SHIFT REGISTER
ADDRESS
COMPARATOR
START/STOP
DETECTOR
REF1
INPUT
LATCH 0
1
OUTPUT
LATCH 0
REF0
DAC0 OUT0
INPUT
LATCH 1
1
OUTPUT
LATCH 1
DAC1 OUT1
DECODE
4
INPUT
LATCH 2
1
OUTPUT
LATCH 2
DAC2 OUT2
INPUT OUTPUT
LATCH 3 LATCH 3
DAC3 OUT3
1
AD0 AD2
AD1
REF2 REF3
Functional Diagrams continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
1 page  
Quad/Octal, 2-Wire Serial 8-Bit DACs
with Rail-to-Rail Outputs
TIMING CHARACTERISTICS
(VDD = 5V ±10%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Serial Clock Frequency
Bus Free Time Between a STOP and a
START Condition
fSCL
tBUF
0
1.3
Hold Time, (Repeated) Start Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated START Condition
Data Hold Time
Data Setup Time
Rise Time of Both SDA and SCL Signals, Receiving
Fall Time of Both SDA and SCL Signals, Receiving
Fall Time of SDA Transmitting (Note 6)
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
tHD, STA
tLOW
tHIGH
tSU, STA
tHD, DAT
tSU, DAT
tR
tF
tF
tSU, STO
Cb
(Note 8)
(Note 9)
(Note 9)
ISINK ≤ 6mA (Note 9)
0.6
1.3
0.6
0.6
0
100
20 + 0.1Cb
20 + 0.1Cb
20 + 0.1Cb
0.6
Pulse Width of Spike Suppressed
tSP (Notes 10, 11)
0
MAX
400
0.9
300
300
250
400
50
UNITS
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
µs
pF
ns
Note 8: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
Note 9: Cb = total capacitance of one bus line in pF. tR and tf measured between 0.3VDD and 0.7VDD.
Note 10: An input filter on the SDA and SCL input suppresses noise spikes less than 50ns.
Note 11: Guaranteed by design.
__________________________________________Typical Operating Characteristics
(VDD = 5V, DAC outputs unloaded, TA = +25°C, unless otherwise noted.)
MAX520
SUPPLY CURRENT vs. TEMPERATURE
10
9 OPERATING MODE OR
8 SHUTDOWN MODE
7
6
5
4
3
2
1
0
-60 -30
0 30 60 90 120 150
TEMPERATURE (°C)
MAX520
REFERENCE INPUT CURRENT vs.
TEMPERATURE (SHUTDOWN MODE)
40
35
VREF = 4V
ONE REF INPUT DRIVEN
30
25
20
15
10
5
0
-60 -30
0 30 60 90 120 150
TEMPERATURE (°C)
MAX520
REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
2
0
-2 VDD = 5V
-4
VREF = 4Vp-p SINE WAVE
CENTERED AT 2.5V
-6
-8
-10
-12
-14
-16
-18
1k
10k 100k 1M
FREQUENCY (Hz)
10M
_______________________________________________________________________________________ 5
5 Page 
Quad/Octal, 2-Wire Serial 8-Bit DACs
with Rail-to-Rail Outputs
START and STOP Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a transmis-
sion with a START condition by transitioning SDA from
high to low while SCL is high (Figure 4). When the mas-
ter has finished communicating with the slave, it issues
a STOP condition by transitioning SDA from low to high
while SCL is high. The bus is then free for another
transmission.
Slave Address
The MAX520/MAX521 each have a 7-bit-long slave
address (Figure 5). The first four bits (MSBs) of the slave
address have been factory programmed and are always
0101. In addition, the MAX521 has the next bit factory
programmed to 0. The logic state of the address input
pins (AD0, AD1, and AD2 of the MAX520; AD0 and AD1
of the MAX521) determine the least significant bits of the
7-bit slave address. These input pins may be connected
to VDD or DGND, or they may be actively driven by TTL
or CMOS logic levels. There are four possible slave
addresses for the MAX521, and therefore a maximum of
four such devices may be on the bus at one time. The
MAX520 has eight possible slave addresses. The eighth
bit (LSB) in the slave address byte should be low when
writing to the MAX520/MAX521.
The MAX520/MAX521 monitor the bus continuously,
waiting for a START condition followed by its slave
address. When a device recognizes its slave address, it
is ready to accept data.
Command Byte and Output Byte
A command byte follows the slave address. Figure 6
shows the format for the command byte. A command
byte is usually followed by an output byte unless it is
the last byte in the transmission. If it is the last byte, all
bits except PD and RST are ignored. If an output byte
follows the command byte, A0–A2 of the command
byte indicate the digital address of the DAC whose
input data latch receives the digital output data. The
data is transferred to the DAC’s output latch during the
STOP condition following the transmission. This allows
all DACs to be updated and the new outputs to appear
simultaneously (Figure 7).
Setting the PD bit high powers down the MAX520/
MAX521 following a STOP condition (Figure 8a). If a
command byte with PD set high is followed by an out-
put byte, the addressed DAC’s input latch will be
updated and the data will be transferred to the DAC’s
output latch following the STOP condition (Figure 8b). If
the transmission’s last command byte has PD high, the
voltage outputs will not reflect the newly entered data
because the DAC will enter power-down mode when
SDA
SCL
START CONDITION
STOP CONDITION
Figure 4. All communications begin with a START condition and
end with a STOP condition, both generated by a bus master.
SLAVE ADDRESS
0
SDA
SCL
10
1 0 or AD2 AD1 AD0 0 ACK
LSB
SLAVE ADDRESS BITS AD2, AD1, AND AD0 CORRESPOND TO THE LOGIC STATE
OF THE ADDRESS INPUT PINS AD2, AD1, AND AD0.
Figure 5. Address Byte
R2
SDA
MSB
R1
R0 RST PD A2 A1 A0 ACK
LSB
SCL
R2, R1, R0: RESERVED BITS. SET TO 0.
RST: RESET BIT, SET TO 1 TO RESET ALL DAC REGISTERS.
PD: POWER-DOWN BIT. SET TO 1 TO PLACE THE DEVICE IN THE 4µA
SHUTDOWN MODE. SET TO 0 TO RETURN TO THE NORMAL
OPERATIONAL STATE.
A2, A1, A0: ADDRESS BITS. DIGITAL ADDRESS FOR DAC0 TO DAC7. DETERMINES
WHICH DAC'S INPUT LATCH RECEIVES THE 8 BITS OF DATA IN
THE NEXT BYTE. A2 IS IGNORED BY THE MAX520.
ACK: ACKNOWLEDGE BIT. THE MAX520/MAX521 PULL SDA LOW DURING THE
9TH CLOCK PULSE.
Figure 6. Command Byte
the STOP condition is detected. When in power-down,
the MAX521’s DAC outputs float, and the MAX520’s
unbuffered outputs look like a 16kΩ resistor to AGND.
In this mode, the supply current is a maximum of 20µA.
A command byte with the PD bit low returns the
MAX520/MAX521 to normal operation following a STOP
condition, and the voltage outputs reflect the current
output-latch contents (Figures 9a and 9b). Because
each subsequent command byte overwrites the previ-
ous PD bit, only the last command byte of a transmis-
sion affects the power-down state.
______________________________________________________________________________________ 11
11 Page | ||
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| PDF Descargar | [ Datasheet MAX521.PDF ] | |
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