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PDF MH32S72BBFA-7 Data sheet ( Hoja de datos )
| Número de pieza | MH32S72BBFA-7 | |
| Descripción | 2 /415 /919 /104-BIT ( 33 /554 /432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM | |
| Fabricantes | Mitsubishi | |
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MITSUBISHI LSIs
MH32S72BBFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DESCRIPTION
The MH32S72BBFA is 33554432 - word x 72-bit
Sy nchronous DRAM stacked structural module. This
consist of thirty -six industry standard 16M x 4
Sy nchronous DRAMs in TSOP.
The stacked structure of TSOP on a card edge dual in-
line package prov ides any application where high
densities and large of quantities memory are required.
This is a socket-ty pe memory module ,suitable f or
easy interchange or addition of module.
FEATURES
Type name
MH32S72BBFA-7
MH32S72BBFA-8
Max.
Frequency
100MHz
100MHz
CLK
Access Time
[latch mode]
(CL = 4)
6ns
6ns
Utilizes industrystandard 16M X 4 Synchronous DRAMs in
TSOP package , industry standard Resister in TSSOP package ,
and industry standard PLL in TSSOP package.
Single 3.3V +/- 0.3V supply
Burst length 1/2/4/8/Full Page (programmable)
Burst type sequential / interleave (programmable)
Column access random
Burst W rite / Single W rite (programmable)
Auto precharge / Auto bank precharge controlled by A10
Auto refresh and Self refresh
LVTTL Interface
4096 refresh cycles every 64ms
Intel specifiation(rev. 1.2)compliant PCB and SPD 1.2A
APPLICATION
Main memoryunit for computers, Microcomputer memory.
85pin 1pin
94pin
95pin
10pin
11pin
124pin 40pin
125pin 41pin
168pin 84pin
MIT-DS-331-0.0
MITSUBISHI
ELECTRIC
16/Jun. /1999 1
1 page  
MITSUBISHI LSIs
MH32S72BBFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BASIC FUNCTIONS
The MH32S72BBFA provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In
addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S
/RAS
/CAS
/WE
CKE
A10
Chip Select : L=select, H=deselect
Command
Command
Command
def ine basic commands
Ref resh Option @ref resh command
Precharge Option @precharge or read/write command
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burs t read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank
is deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
term inates burs t read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
PEFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
MIT-DS-331-0.0
MITSUBISHI
ELECTRIC
16/Jun. /1999 5
5 Page 
MITSUBISHI LSIs
MH32S72BBFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE FOR CKE
Current State
CK
n-1
CK
n
SELF -
HX
REFRESH*1 L H
LH
LH
LH
LH
POWER
DOWN
LL
HX
LH
LL
ALL BANKS H H
IDLE*2
HL
HL
HL
HL
HL
HL
ANY STATE
other than
listed above
L
H
H
L
L
X
H
L
H
L
/S /RAS /CAS /WE Add
Action
X X X X X INVALID
H X X X X Exit Self-Refresh(Idle after tRC)
L H H H X Exit Self-Refresh(Idle after tRC)
L H H L X ILLEGAL
L H L X X ILLEGAL
L L X X X ILLEGAL
X X X X X NOP(Maintain Self-Refresh)
X X X X X INVALID
X X X X X Exit Power Down to Idle
X X X X X NOP(Maintain Self-Refresh)
X X X X X Refer to Function Truth Table
L L L H X Enter Self-Refresh
H X X X X Enter Power Down
L H H H X Enter Power Down
L H H L X ILLEGAL
L H L X X ILLEGAL
L L X X X ILLEGAL
X X X X X Refer to Current State = Power Down
X X X X X Refer to Function Truth Table
X X X X X Begin CK0 Suspend at Next Cycle*3
X X X X X Exit CK0 Suspend at Next Cycle*3
X X X X X Maintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High trans ition will re-enable CK and other inputs asynchronously.
A m inimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only form the All banks idle State.
3. Must be legal command.
MIT-DS-331-0.0
MITSUBISHI
ELECTRIC
16/Jun. /1999 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MH32S72BBFA-7.PDF ] | |
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