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PDF MH2S64CZTJ-15 Data sheet ( Hoja de datos )
| Número de pieza | MH2S64CZTJ-15 | |
| Descripción | 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH2S64CZTJ/CWZTJ-12,-15,-1539
134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH2S64CZTJ/CWZTJ is 2097152-word by
64-bit Synchronous DRAM module. This consists of
eight industry standard 2Mx8 Synchronous DRAMs
in TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
FEATURES
Frequency
CLK Access Time
(Component SDRAM)
-12 83MHz
8ns(CL=3)
-15
67MHz
9.5ns (CL=2)
85pin 1pin
94pin
95pin
10pin
11pin
-1539
67MHz
9ns (CL=3)
Utilizes industry standard 2M x 8 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
single 3.3V±0.3V power supply
124pin 40pin
125pin 41pin
Clock frequency 83MHz/67MHz
Fully synchronous operation referenced to clock rising
edge
Dual bank operation controlled by BA(Bank Address)
/CAS latency- 1/2/3(programmable)
Burst length- 1/2/4/8(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
168pin 84pin
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
APPLICATION
main memory or graphic memory in computer systems
SPD table
Byte No.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 126 127
MH2S64CZTJ/CWZTJ-12 80 08 04 0C 09 01 40 00 01 C0 80 00 80 00 06 01 05 02 06 01 01 83 06
MH2S64CZTJ/CWZTJ-15 80 08 04 0C 09 01 40 00 01 F0 95 00 80 00 06 01 05 02 06 01 01 66 06
MH2S64CZTJ/CWZTJ-1539 80 08 04 0C 09 01 40 00 01 F0 90 00 80 00 04 01 05 02 04 01 01 66 04
MIT-DS-0019-0.4
MITSUBISHI
ELECTRIC
Oct.28.1996
( 1 / 45 )
1 page  
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH2S64CZTJ/CWZTJ-12,-15,-1539
134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM
PIN FUNCTION
CK
(CK0 & CK1)
CKE
Input
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
/S
(/S0 & /S2)
/RAS,/CAS,/WE
Input
Input
Chip Select: When /S is high,any command means
No Operation.
Combination of /RAS,/CAS,/WE defines basic commands.
A0-10
BA
DQ0-63
DQMB0-7
Vdd,Vss
Input
A0-10 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-10.The Column
Address is specified by A0-8.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
Input
Bank Address:BA is not simply BA.BA specifies the bank
to which a command is applied.BA must be set with
ACT,PRE,READ,WRITE commands
Input/Output
Data In and Data out are referenced to the rising edge of
CK
Input
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is high
in burst read,Dout is disabled at the next but one cycle.
Power Supply Power Supply for the memory mounted module.
SLA Input Serial clock for serial PD
SDA
Output Serial data for serial PD
SA0-3
Input Address input for serial PD
MIT-DS-0019-0.4
MITSUBISHI
ELECTRIC
( 5 / 45 )
Oct.28.1996
5 Page 
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH2S64CZTJ/CWZTJ-12,-15,-1539
134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State
RE-
FRESHING
MODE
REGISTER
SETTING
/S /RAS /CAS /WE Address
Command
Action
H X X XX
DESEL NOP(Idle after tRC)
L H H HX
NOP
NOP(Idle after tRC)
L H H L BA
TBST
ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL
L L H H BA,RA
ACT
ILLEGAL
L L H L BA,A10
PRE/PREA ILLEGAL
L L L HX
REFA
ILLEGAL
Op-Code,
LLLL
Mode-Add
MRS
ILLEGAL
H X X XX
DESEL NOP(Idle after tRSC)
L H H HX
NOP
NOP(Idle after tRSC)
L H H L BA
TBST
ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL
L L H H BA,RA
ACT
ILLEGAL
L L H L BA,A10
PRE/PREA ILLEGAL
L L L HX
REFA
ILLEGAL
Op-Code,
LLLL
Mode-Add
MRS
ILLEGAL
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
MIT-DS-0019-0.4
MITSUBISHI
ELECTRIC
( 11 / 45 )
Oct.28.1996
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MH2S64CZTJ-15.PDF ] | |
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