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ON Semiconductor |
MC14022B
Octal Counter
The MC14022B is a four–stage Johnson octal counter with built–in
code converter. High–speed operation and spike–free outputs are
obtained by use of a Johnson octal counter design. The eight decoded
outputs are normally low, and go high only at their appropriate octal
time period. The output changes occur on the positive–going edge of
the clock pulse. This part can be used in frequency division
applications as well as octal counter or octal decode display
applications.
• Fully Static Operation
• DC Clock Input Circuit Allows Slow Rise Times
• Carry Out Output for Cascading
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
• Pin–for–Pin Replacement for CD4022B
• Triple Diode Protection on All Inputs
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)
Symbol
Parameter
Value
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
– 0.5 to +18.0
– 0.5 to VDD + 0.5
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10
Unit
V
V
mA
PD Power Dissipation,
per Package (Note 2.)
500 mW
TA Ambient Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8–Second Soldering)
– 55 to +125
– 65 to +150
260
°C
°C
°C
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v vhigh–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
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PDIP–16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC14022BCP
AWLYYWW
1
SOIC–16
D SUFFIX
CASE 751B
16
14022B
AWLYWW
1
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14022BCP
PDIP–16
2000/Box
MC14022BD
SOIC–16
2400/Box
MC14022BDR2 SOIC–16 2500/Tape & Reel
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14022B/D
MC14022B
PIN ASSIGNMENT
Q1 1
Q0 2
16 VDD
15 R
Q2 3
Q5 4
Q6 5
NC 6
Q3 7
VSS 8
14 C
13 CE
12 Cout
11 Q4
10 Q7
9 NC
NC = NO CONNECTION
BLOCK DIAGRAM
CLOCK 14
CLOCK
ENABLE 13
RESET 15
VDD = PIN 16
VSS = PIN 8
NC = PIN 6, 9
Q0 2
Q1 1
Q2 3
Q3 7
Q4 11
Q5 4
Q6 5
Q7 10
Cout 12
FUNCTIONAL TRUTH TABLE
(Positive Logic)
Clock
Clock Enable Reset Output=n
0 X0
n
X 10
n
0 0 n+1
X0
n
1 0 n+1
X 0n
X X 1 Q0
X = Don’t Care. If n < 4 Carry = 1,
Otherwise = 0.
CLOCK
14
13
CLOCK
ENABLE
15
RESET
LOGIC DIAGRAM
11 1 5 7
Q4 Q1 Q6 Q3
VDD
VSS
CQ CQ
CC
DRQ DRQ
CQ
C
D RQ
CARRY
C Q 12
C
D RQ
Q0 Q5 Q2 Q7
2 4 3 10
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