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PDF MC10E197 Data sheet ( Hoja de datos )
| Número de pieza | MC10E197 | |
| Descripción | DATA SEPARATOR | |
| Fabricantes | ON Semiconductor | |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
Data Separator
MC10E197
The MC10E197 is an integrated data separator designed for use in
high speed hard disk drive applications. With data rate capabilities of up
to 50Mb/s the device is ideally suited for today’s and future
state-of-the-art hard disk designs.
The E197 is typically driven by a pulse detector which reads the
magnetic information from the storage disk and changes it into ECL
pulses. The device is capable of operating on both 2:7 and 1:7 RLL
coding schemes. Note that the E197 does not do any decoding but rather
prepares the disk data for decoding by another device.
For applications with higher data rate needs, such as tape drive
systems, the device accepts an external VCO. The frequency capability
of the integrated VCO is the factor which limits the device to 50Mb/s.
A special anti-equivocation circuit has been employed to ensure timely
lock-up when the arriving data and VCO edges are coincident.
Unlike the majority of the devices in the ECLinPS family, the E197 is
available in only 10H compatible ECL. The device is available in the
standard 28-lead PLCC.
Since the E197 contains both analog and digital circuitry, separate
supply and ground pins have been provided to minimize noise coupling
inside the device. The device can operate on either standard negative
ECL supplies or, as is more common, on positive voltage supplies.
• 2:7 and 1:7 RLL Format Compatible
• Fully Integrated VCO for 50Mb/s Operation
• External VCO Input for Higher Operating Frequency
• Anti-equivocation Circuitry to Ensure PLL Lock
RDEN
LOGIC DIAGRAM
DATA SEPARATOR
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
REFCLK
CAP1
CAP2
VCOIN
EXTVCO
ENVCO
RAWD
INTERNAL
VCO
VCO
MUX
PHASE FREQUENCY
DETECTOR
DATA
PHASE
DETECTOR
PHASE
DETECTOR
MUX
CHARGE
PUMP
CURRENT-
SOURCES
PUMPUP
PUMPDN
RSETUP
RSETDN
ACQ
TYPE
ACQUISITION
CIRCUITRY
CLOCK &
DATA
BUFFER
RDATA
RDCLK
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
12/93
© Motorola, Inc. 1996
2–1
REV 2
1 page  
MC10E197
Idle Mode
In the absence of data or when the drive is writing to the disk,
PLL servoing is accomplished by pulling the read enable line
(RDEN) low and providing a reference clock via the REFCLK
pins. The condition whereby RDEN is low selects the
Phase/Frequency detector (Figure 1) and the 10E197 is said
to be operating in the “idle mode”. In order to function as a
frequency detector the input waveform must be periodic. The
pump up and pump down pulses from the Phase/Frequency
detector will have the same frequency, phase and pulse width
only when the two clocks that are being compared have their
positive edges aligned and are of the same frequency.
As with the data phase detector, by using suitable external
filter circuitry, a VCO input control signal can be generated by
inverting the pump down signal, summing the inverted signal
with the pump up signal and averaging the result. The polarity
of this control signal is defined as zero when all positive edges
of both clocks are coincident. For the case in which the
frequencies of the two clocks are the same but the clock edges
of the reference clock are slightly advanced with respect to the
VCO clock, the control clock is defined to have a positive
polarity. A control signal with negative polarity occurs when
the edges of the reference clock are delayed with respect to
those of the VCO. If the frequencies of the two clocks are
different, the clock with the most edges per unit time will initiate
the most pulses and the polarity of the detector will reflect the
frequency error. Thus, when the reference clock is high in
frequency than the VCO clock the polarity of the control signal
is positive; whereas a control signal with negative polarity
occurs when the frequency of the reference clock is lower than
the VCO clock.
Phase-Lock Loop Theory
Introduction
Phase lock loop (PLL) circuits are fundamentally feedback
systems used to synchronize the frequency of an oscillator to
an incoming signal. In addition to frequency synchronization,
the PLL circuitry is designed to minimize the phase difference
between the system input and output signals. A block diagram
of a feedback control system is shown in Figure 1.
where:
A(s) is the product of the feed-forward transfer functions.
Xi(s)
+
R
Xe(s)
A(s)
–
Xo(s)
β(s)
Fi
PHASE
DETECTOR
Kf
LOOP FILTER
F(s)
VCO
Ko
s
Fo
Figure 2. Phase Lock Loop Block Diagram
The closed loop transfer function is:
Xo(s) =
Xi(s)
Kφ
Ko
s
F(s)
1 + Kφ
Ko
s
F(s)
where:
Kφ= the phase detector gain.
Ko= the VCO gain. Since the VCO introduces a
pole at the origin of the s-plane, Ko is divided
by s.
F(s) = the transfer function of the loop filter.
Figure 1. Feedback System
β(s) is the product of the feedback transfer functions.
The transfer function for this closed loop system is
Xo(s) =
Xi(s)
A(s)
1 + A(s)β(s)
Typically, phase lock loops are modeled as feedback
systems connected in a unity feedback configuration (β(s)=1)
with a phase detector, a VCO (voltage controlled oscillator),
and a loop filter in the feed-forward path, A(s). Figure 2
illustrates a phase lock loop as a feedback control system in
block diagram form.
The 10E197 is designed to implement the phase detector
and VCO functions in a unity feedback loop, while allowing the
user to select the desired filter function.
Gain Constants
As mentioned, each of the three sections in the phase lock
loop block diagram has an associated open loop gain
constant. Further, the gain constant of the filter circuitry is
composed of the product of three gain constants, one for each
filter subsection. The open loop gain constant of the
feed-forward path is given by
Kol = Kφ * Ko * K1 * Kl * Kd
eqt. 1
and obtained by performing a root locus analysis.
Phase Detector Gain Constant
The gain of the phase detector is a function of the operating
mode and the data pattern. The 10E197 provides data
ECLinPS and ECLinPS Lite
DL140 — Rev 4
2–5
MOTOROLA
5 Page 
MC10E197
From Equation 7 the value for the other resistors associated
with the integrator op-amp are set equal to RA:
RlA = RA = 5.11kΩ
Voltage Divider Subsection
The element values for the voltage divider network are
calculated using the relationships presented in Equations 8,
9, and 10 with the constraint that this divider network must
produce a voltage that lies within the range 1.3V + VEE to 2.6V
+ VEE.
Restating Equation 9,
Kd =
Kol
Kφ * Ko * K1 * Kl
From the root locus analysis Kol is determined to be:
Kol
=
1.585
e51
V
mA sec3
From Equation 3
1
K1 = A1 * CIN
and the gain constant K1 is:
V
K1 = 8.90 e21 mA sec
From Equation 5
Kl = Al *
RA
RlA
and the gain constant Kl is:
Kl = 2.48
e15
V
V
Having determined the gain constant Kd , the value of Rv, is
selected such that the constraints Rv > Ro and:
Kd Ro
2π p2 = Ro + Rv
are fulfilled. The pole position P2 is determined from the root
locus analysis to be:
P2 = – 3.06MHz
Hence, Rv is selected to be:
Rv = 2.15kΩ
and Ro is calculated to be:
Ro = 700Ω
Finally, using Equation 8a:
1
Cd = Rv Kd
eqt. 8a
the capacitor value, Cd is:
Cd = 98pF
Note that the voltage divider section can be used to set the
gain, but the designer is cautioned to be sure the input
value to VCOIN is within the correct range.
Component Scaling
As mentioned, these design equations were developed for
a data rate of 23 Mbit/sec. If the data rate is different from the
nominal design value the reactive elements must be scaled
accordingly. The following equations are provided to facilitate
scaling and were derived with the assumptions that a 2:7
coding scheme is used and that the RDCLK signal is twice the
frequency of the data clock.
46
CIN = 278 * f
46
Cd = 98 * f
(pF)
(pF)
eqt. 11
eqt. 12
where f is the RDCLK frequency in MHz.
Example for an 11 Mbit/sec Data Rate
As an example of scaling, assume the given filter and a 2:7
code are used but the data rate is 11Mbit/sec. The dynamic
pole positions, and therefore the bandwidth of the loop filter,
are a function of the data rate. Thus a slower data rate will
force the dynamic poles and the bandwidth to move to a lower
frequency. From Equation 11 the value of CIN is:
CIN = 581pF
and from Equation 12 the value of Cd is:
Cd = 205pF
Thus the element values for the filter are:
Filter Input Subsection:
CIN = 581pF
R1 = 1kΩ
Integrator Subsection:
CA = 0.1µF
RA = 5.11kΩ
RlA = 5.11kΩ
Voltage Divider Subsection:
Cd = 205pF
Rv = 2.15kΩ
Ro = 700kΩ
ECLinPS and ECLinPS Lite
DL140 — Rev 4
2–11
MOTOROLA
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MC10E197.PDF ] | |
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