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PDF SMJ44400 Data sheet ( Hoja de datos )
| Número de pieza | SMJ44400 | |
| Descripción | 1M x 4 DRAM DYNAMIC RANDOM-ACCESS MEMORY | |
| Fabricantes | ETC | |
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Austin Semiconductor, Inc.
DRAM
SMJ44400
1M x 4 DRAM
DYNAMIC RANDOM-ACCESS
MEMORY
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-90847
• MIL-STD-883
FEATURES
• Organized 1,048,576 x 4
• Single +5V ±10% power supply
• Enhanced Page-Mode operation for faster memory access
P Higher data bandwidth than conventional page-mode
parts
P Random Single-Bit Access within a row with a column
address
• CAS\-Before-RAS\ (CBR) Refresh
• Long Refresh period: 1024-cycle Refresh in 16ms (Max)
• 3-State unlatched Output
• Low Power Dissipation
• All Inputs/Outputs and Clocks are TTL Compatible
• Processing to MIL-STD-883, Class B available
OPTIONS
• Timing
80ns access
100ns access
120ns access
MARKING
-80
-10
-12
• Package(s)
Ceramic DIP (400mils)
Ceramic Flatpack
JD No. 113
HR No. 308
• Operating Temperature Ranges
Military (-55oC to +125oC) M
GENERAL DESCRIPTION
The SMJ44400 is a series of 4,194,304-bit dynamic ran-
dom-access memories (DRAMs), organized as 1,048,576
words of four bits each. This series employs state-of-the-art
technology for high performance, reliability, and low-power
operation.
The SMJ44400 features maximum row access times of
80ns, 100ns, and 120ns. Maximum power dissipation is as
low as 360mW operating and 22mW standby.
All inputs and outputs, including clocks, are compatible
with Series 54 TTL. All addressses and data-in lines are latched
on-chip to simplify system design. Data out is unlatched to
allow greater system flexibility.
PIN ASSIGNMENT
(Top View)
20-Pin DIP (JD)
20-Pin Flatpack (HR)
(400 MIL)
DQ1
DQ2
W\
RAS\
A9
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
20 Vss
19 DQ4
18 DQ3
17 CAS\
16 OE\
15 A8
14 A7
13 A6
12 A5
11 A4
Pin Name
Function
A0 - A9 Address Inputs
CAS\ Column-Address Strobe
DQ1 - DQ4 Data Inputs/Outputs
OE\ Output Enable
RAS\ Row-Address Strobe
W\ Write Enable
Vcc 5V Supply
Vss Ground
The SMJ44400 is offered in a 400-mil, 20-pin ceramic
side-brazed dual-in-line package (JD suffix) and a 20-pin
ceramic flatpack (HR suffix) that are characterized for
operation from -55°C to +125°C.
OPERATION
Enhanced Page Mode
Enhanced page-mode operation allows faster memory
access by keeping the same row address while selecting
random column addresses. The time for row-address setup
and hold and address multiplex is eliminated. The maximum
number of columns that can be accessed is determined by the
maximum RAS\ low time and the CAS\ page cycle time used.
With minimum CAS\ page cycle time, all 1024 columns
specified by column addresses A0 through A9 can be accessed
without intervening RAS\ cycles.
Unlike conventional page-mode DRAMs, the column-
address buffers in this device are activated on the
For more products and information
please visit our web site at
www.austinsemiconductor.com
SMJ44400
Rev. 2.0 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
1 page  
Austin Semiconductor, Inc.
DRAM
SMJ44400
ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(-55oC<TA<125oC or -40oC to +85oC; Vcc = 5V +10%)
SYM
PARAMETER
TEST CONDITIONS
-8 -10 -12
MIN MAX MIN MAX MIN MAX UNIT
VOH High-level output voltage
IOH = -5mA
2.4 2.4 2.4
V
VOL Low-level output voltage
IOL = 4.2mA
0.4 0.4 0.4 V
II Input current (leakage)
IO Output current (leakage)
ICC1 Read - or write-cycle current1
ICC2 Standby current
VCC = 5.5V, VI = 0V to 6.5V, All
other pins = 0V to VCC
VCC = 5.5V, VO = 0V to VCC,
CAS\ High
VCC = 5.5V, Minimum cycle
After 1 memory cycle,
RAS\ and CAS\ High,
VIH = 2.4V
±10 ±10 ±10 µA
±10 ±10 ±10 µA
85 80 70 mA
4 4 4 mA
Average refresh current
ICC3 (RAS\ only, or CBR\)1
VCC = 5.5V, Minimum cycle,
RAS\ cycling,
CAS\ High (RAS\ only),
RAS\ Low after CAS\ Low (CBR)
85 75 65 mA
ICC4 Average page current2
VCC = 5.5V, tPC = minimum,
RAS\ Low, CAS\ cycling
50 40 35 mA
CAPACITANCE (f = 1MHz)3
SYM
Ci(A)
Ci(RC)
Ci(W)
CO
PARAMETER
Input capacitance, address inputs
Input capacitance, strobe inputs
Input capacitance, write-enable inputs
Output capacitance
MAX
7
10
10
10
UNIT
pF
pF
pF
pF
SWITCHING CHARACTERISTICS (-55oC<TA<125oC or -40oC to +85oC; Vcc = 5V +10%)
SYM
PARAMETERS
-8
MAX
-10
MAX
-12
MAX
UNIT
tAA Access time from column address
40 45 55 ns
tCAC Access time from CAS\ low
20 25 30 ns
tCPA Access time from column precharge
45 50 55 ns
tRAC Access time from RAS\ low
80 100 120 ns
tOEA Access time from OE\ low
20 25 30 ns
tOFF Output disable time after CAS\ High4
20 25 30 ns
tOEZ Output disable tiem after OE\ High4
20 25 30 ns
NOTES:
1. Measured with a maximum of one address change while RAS\ = VIL.
2. Measured with a maximum of one address change while CAS\ = VIH.
3. VCC = 5V ±0.5V and the bias on the pins under test is 0V. Capacitance is sampled only at initial design and after any major change.
4. tOFF and tOEZ are specified when the output is no longer driven. The outputs are disabled by bringing either OE\ or CAS\ High.
SMJ44400
Rev. 2.0 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
5 Page 
Austin Semiconductor, Inc.
READ-WRITE CYCLE TIMING
DRAM
SMJ44400
(1)
NOTES:
1. Valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an invalid-data state prior to the specified access tiems as the outputs are driven when
CAS\ and OE\ are low.
SMJ44400
Rev. 2.0 10/01
11
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11 Page | ||
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| PDF Descargar | [ Datasheet SMJ44400.PDF ] | |
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