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PDF TP5335 Data sheet ( Hoja de datos )
| Número de pieza | TP5335 | |
| Descripción | P-Channel Enhancement-Mode Vertical DMOS FETs | |
| Fabricantes | Supertex Inc | |
| Logotipo |  |
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Supertex inc.
TP5335
P-Channel Enhancement-Mode
Vertical DMOS FET
Features
►► High input impedance and high gain
►► Low power drive requirement
►► Ease of paralleling
►► Low CISS and fast switching speeds
►► Excellent thermal stability
►► Integral source-drain diode
►► Free from secondary breakdown
Applications
►► Logic level interfaces - ideal for TTL and CMOS
►► Solid state relays
►► Analog switches
►► Power management
►► Telecom switches
General Description
The Supertex TP5335 is a low threshold enhancement-
mode (normally-off) transistor utilizing an advanced vertical
DMOS structure and Supertex’s well-proven silicon-gate
manufacturing process. This combination produces a device
with the power handling capabilities of bipolar transistors
and with the high input impedance and positive temperature
coefficient inherent in MOS devices. Characteristic of all
MOS structures, this device is free from thermal runaway and
thermally-induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
high breakdown voltage, high input impedance, low input
capacitance, and fast switching speeds are desired.
Ordering Information
Part Number Package Option
Packing
TP5335K1-G TO-236AB (SOT-23) 3000/Reel
-G denotes a lead (Pb)-free / RoHS compliant package.
Contact factory for Wafer / Die availablity.
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.
Absolute Maximum Ratings
Parameter
Value
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
BVDSS
BVDGS
±20V
Operating and storage temperature -55OC to +150OC
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
Typical Thermal Resistance
Package
θja
TO-236AB (SOT-23)
203OC/W
Product Summary
BVDSS/BVDGS
RDS(ON)
(max)
-350V
30Ω
Pin Configuration
DRAIN
VGS(th)
(max)
-2.4V
SOURCE
GATE
TO-236AB (SOT-23)
Product Marking
P3SW
W = Code for week sealed
= “Green” Packaging
Package may or may not include the following marks: Si or
TO-236AB (SOT-23)
Doc.# DSFP-TP5335
B081913
Supertex inc.
www.supertex.com
1 page | ||
| Páginas | Total 3 Páginas | |
| PDF Descargar | [ Datasheet TP5335.PDF ] | |
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