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PDF SL3ICS30 Data sheet ( Hoja de datos )
| Número de pieza | SL3ICS30 | |
| Descripción | UCODE HSL | |
| Fabricantes | NXP Semiconductors | |
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SL3ICS3001
UCODE HSL
Rev. 3.1 — 9 July 2012
072831
Product data sheet
COMPANY PUBLIC
1. General description
The UCODE HSL IC, SL3ICS3001 (UCODE High frequency Smart Label) is a dedicated
chip for passive smart tags and labels, especially for supply chain management and
logistics applications in the US, where operating distances of several meters can be
realized. Further, the UCODE HSL technology platform is also designed for operation
under European regulations.
This integrated circuit is the first member of a product family of smart label ICs targeted to
be compliant with the future ISO standards 18000-4 and 18000-6 for item management.
The UCODE HSL system offers the possibility of operating labels simultaneously in the
field of the interrogator antenna (Anticollision, Collision Arbitration).
The UCODE HSL family of ICs is especially designed for long range applications.
The tag requires no internal power supply. Its contactless interface generates the power
supply via the antenna circuit by propagative energy transmission from the interrogator
(read/write device), while the system clock is generated by an on-board oscillator. The
contactless interface demodulates data transmitted from the interrogator to the UCODE
HSL based tag, and further modulates the electromagnetic field provided by the
interrogator for data transmission from the UCODE HSL based tag to the interrogator.
A generic RFID system consists of an interrogator (base station) that runs the RFID
protocol, as well as one or more tags. The tag itself includes an SL3ICS3001 chip and an
antenna tuned to the carrier frequency of the interrogator, and a package to hold the chip
and antenna together.
When placed in the RF field of an interrogator, a SL3ICS3001 based tag will begin to
power up. If the field is strong enough, the tag IC will execute a power-on reset and will be
ready to receive commands. Each command begins with a preamble and start delimiter
that, taken together, enable the tag to perform clock and data recovery on the incoming
signal. Data to and from the tag is checked for errors using a CRC. Therefore, CRC fields
are present in all interrogator commands and in all tag responses. Additional data
protection is provided by Manchester encoding on the forward (interrogator to tag) link
and FM0 encoding on the return (tag to interrogator) link.
The interrogator can perform a number of functions on tags in its field. For example, the
interrogator can send a command sequence, which allows it to identify multiple tags in its
RF field simultaneously. Alternatively, it can select a subset of the tags in the field based
on tag memory contents. It can also read data stored on a tag in its field, as well as write
data to such a tag. In addition, it can simultaneously write data to an arbitrary subset of the
tags in the field.
1 page  
NXP Semiconductors
SL3ICS3001
UCODE HSL
5. Block diagram
The SL3ICS3001 IC consists of three major blocks:
- Analog RF Interface
- Digital Controller
- EEPROM
The analog part provides stable supply voltage and demodulates data received from the
interrogator for processing by the digital part. Further, the modulation transistor of the
analog part transmits data back to the interrogator.
The digital section includes the state machines, processes the protocol and handles
communication with the EEPROM, which contains a unique ID and user data.
ANTENNA
ANALOGUE
RF INTERFACE
PAD
VREG
DIGITAL CONTROL
VDD
ANTICOLLISION
RECT DEMOD
data
in
READ/WRITE
CONTROL
MOD
ACCES CONTROL
PAD
data
out
EEPROM INTERFACE
CONTROL
R/W
EEPROM
MEMORY
Fig 1. Block diagram
RF INTERFACE
CONTROL
SEQUENCER
CHARGE PUMP
001aai335
6. Pinning information
For pinning details please refer to Ref. 7 “Data sheet addendum”.
SL3ICS3001_072831
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.1 — 9 July 2012
072831
© NXP B.V. 2012. All rights reserved.
5 of 54
5 Page 
NXP Semiconductors
SL3ICS3001
UCODE HSL
8.3 Flags
The flag byte can be accessed by the GROUP_SELECT_yy_FLAGS and
GROUP_UNSELECT_yy_FLAGS commands. In the BYTE_MASK (see Section 11.2.1.2)
of those commands a matching criteria can be set. As only the two least significant bit of
the flag byte are used in this IC all others are zero (logic 0).
The SL3ICS30 supports a field of 8 flags. This field is called FLAGS.
Table 6. Flags
Bit
FLAG1 (LSB)
FLAG2
FLAG3
FLAG4
FLAG5
FLAG6
FLAG7
FLAG8 (MSB)
Name
DE_SB (Data_Exchange Status Bit)
WRITE_OK
0 (RFU)
0 (RFU)
0 (RFU)
0 (RFU)
0 (RFU)
0 (RFU)
8.3.1 Data_Exchange status bit
The tag sets this bit when the tag goes into the DATA_EXCHANGE state and keeps it set
unless it moves into the POWER-OFF state. When the DE_SB is set and the tag comes
into the POWER-OFF state, then the tag triggers a timer that will reset the DE_SB bit after
tDE_SB.
When the tag goes into the READY state after POWER-OFF state and the DE_SB bit is
still set, the timer is reset and DE_SB stays set.
When the tag receives the INITIALIZE command, then it reset the DE_SB bit immediately.
8.3.2 WRITE_OK
LSB+1 (Bit 1) of the flag byte. This bit indicates that a previous write operation was done
without any problems. If WRITE_OK is set, the last programming cycle of the EEPROM
was done properly.
The WRITE_OK bit is reset by any inadequate EEPROM write cycle or a voltage supply
interruption (see Section 9.7). Further, it is reset latest at the begin of the second
command following a write access to the EEPROM.
NOTE: To be absolute sure that the programming process was done correct, the data
needs to be verified with an additional read command.
SL3ICS3001_072831
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.1 — 9 July 2012
072831
© NXP B.V. 2012. All rights reserved.
11 of 54
11 Page | ||
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| PDF Descargar | [ Datasheet SL3ICS30.PDF ] | |
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