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PDF SL34118 Data sheet ( Hoja de datos )
| Número de pieza | SL34118 | |
| Descripción | Voice Switched Speakerphone Circuit | |
| Fabricantes | System Logic Semiconductor | |
| Logotipo |  |
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SL34118
Voice Switched Speakerphone Circuit
The SL34118 Voice Switched Speakerphone Circuit incorporates
the necessary amplifiers, attenuators, level detectors, and control
algorithm to form the heart of a high quality hands-free speakerphone
system. Included are a microphone amplifier with adjustable gain and
MUTE control, Transmit and Receive attenuators which operate in a
complementary manner, level detectors at both input and output of
both attenuators, and background noise monitors for both the transmit
and receive channels. A Dial Tone Detector prevents the dial tone
from being attenuated by the Receive background noise monitor
circuit. Also included are two line driver amplifiers which can be used
to form a hybrid network in conjunction with an external coupling
transformer. A high pass filter can be used to filter out 60 Hz noise in
the reseive channel, or for other filtering functions. A Chip Disable pin
permits powering down the entire circuit to conserve power on long
loops where loop current is at a minimum.
The SL34118 may be operated from a power supply, or it can be
powered from the telephone line, requiring typically 5.0 mA. The
SL34118 can be interfaced directly to Tip and Ring (through a coupling
transformer) for stand-alone operation, or it can be used in
conjunction with a handset speech network and or other features of a
featurephone.
• Improved Attenuator Gain Range: 52 dB Between Transmit and
Receive
• Low Voltage Operation for Line-Powered Applications (3.0-6.5 V)
• 4 Point Signal Sensing for Improved Sensitivity
• Background Noise Monitors for Both Transmit and Receive Paths
• Microphone Amplifier Gain Set by External Resistors - Mute
Function Included
• Chip Disable for Active Standby Operation
• On Board Filter Pinned-Out for User Deined Function
• Dial Tone Detector to Inhibit Receive Idle Mode During Dial Tone
Presence
ORDERING INFORMATION
SL34118N Plastic
SL34118D SOIC
TA = -25° to 70° C for all packages
PIN ASSIGNMENT
SLS
System Logic
Semiconductor
1 page  
SL34118
ATTENUATOR CONTROL BLOCK
The Attenuator Control Block has the seven
inputs described above:
- Tthe output of the comparator operated by RLO2
and TLO2 (microphone/speaker side) - designated
C1.
- The output of the comparator operated by RLO1
and TLO1 (Tip/Ring) side) - designated C2.
- The output of the transmit background noise
monitor - designated C3.
- The output of the receive background noise
monitor - designated C4.
- The volume control.
- The dial tone detector.
- The AGC circuit.
The single output of the Control Block controls
the two attenuators. The effect of C1-C4 is as follows:
Inputs
Output
C1 C2 C3 C4
Mode
Tx Tx
1
X Transmit
Tx Rx
Y
Y Fast Idle
Rx Tx
Y
Y Fast Idle
Rx Rx
X
1
Receive
Tx Tx
0
X Slow Idle
Tx Rx
0
0 Slow Idle
Rx Tx
0
0 Slow Idle
Rx Rx
X
0 Slow Idle
X = Don’t Care; Y = C3 and C4 are not both 0
A definition of the above terms:
1) “Transmit” means the transmit attenuator is
fully on (+6.0 dB), and the receive attenuator is
at max. attenuation (-46 dB).
2) “Receive” means both attenuators are
controlled by the volume control. At max.
volume, the receive attenuator is fully on
(6.0 dB), and the transmit attenuator is at max.
attenuation (-46 dB).
3) “Fast Idle” means both transmit and receive
speech are present in approximately equal levels.
The attenuators are quickly switched (30 ms) to
idle until one speech level dominates the other.
4) “Slow Idle” means speech has ceassed in both
transmit and receive path. The attenuators are
then slowly switched (1 second) to the idle
mode.
5) Switching to the full transmit or receive modes
from any other mode is at the fast rate (30 ms).
A summary of the truth table is as follows:
1) The circuit will switch to transmit if: a) both
transmit level detectors sense higher signal levels
relative to the respective receive level detectors (TLI1
versus RLI1, TLI2 versus RLI2), and b) the transmit
background noise monitor indicates the presence of
speech.
2) The circuit will switch to receive if: a) both
receive level detectors sense higher signal levels
relative to the respective transmit level detectors, and
b) the receive background noise monitor indicates the
presence of speech.
3) The circuit will switch to the fast idle mode if the
level detectors disagree on the relative strengths of
the signal levels, and at least one of the background
noise monitors indicates speech. For example,
refferring to the Expanded Logic Diagram (Figure 8), if
there is sufficient signal at the microphone amp
output (TLI2) to override the speaker signal (RLI2),
and there is sufficient signal at the receive input
(RLI1) to override the signal at the hybrid output
(TLI1), and either or both background monitors
indicate speech, then the circuit will be in the fast idle
mode. Two conditions which can cause the fast idle
mode to occur are a) when both talkers are attempting
to gain control of the system by talking at the same
time, and b) when one talker is in a very noisy
environment, forcing the other talker to continually
override that noise level. In general, the fast idle mode
will occur infrequently.
4) The circuit will switch to the slow idle mode
when a) both talkers are quiet (no speech present), or
b) when one talker’s speech level is continuously
overriden by noise at the other speaker’s location.
The time required to switch the circuit between
transmit, receive, fast idle and slow idle is determined
in part by the components at the CT pin (Pin 14). A
schematic of the CT circuitry is shown in Figure 4 and
operates as follows:
- RT is typically 120 kΩ, and CT typically 5.0 µF.
- To switch to the receive mode, I1 is turned on (I2 is
off), charging the external capacitor to +240 mV
above VB. (An internal clamp prevents further
charging of the capacitor.)
- To switch to the transmit mode, I2 is turned on (I1
is off) bringing down the voltage on the capacitor
to -240 mV with respect to VB.
- To switch to idle quickly (fast idle), the current
sources are turned off, and the internal 2.0 kΩ
resistor is switched in, discharging the capacitor
to VB with a time constant = 2.0 KΩ x CT.
- To switch to idle slowly (slow idle), the current
sources are turned off, the switch at the 2.0 kΩ
resistor is open, and the capacitor discharges to
VB through the external resistor RT with a time
constant = RT x CT.
SLS
System Logic
Semiconductor
5 Page 
SL34118
ELECTRICAL CHARACTERISTICS(TA = -25 to +70°C, VCC = 5.0 V , CD = 0.8 V, unless noted)
Guaranteed
Symbol
Parameter
Test Conditions
Limits
Unit
Min Max
HYBRID AMPLIFIERS
HVOS HTO - Offset
VHTO- - VB,
Freedback R= 51 KΩ
VB - 25 VB +25 mV
HBVOS HTO - to HTO+ Offset
Freedback R= 51 KΩ
AVOLH Open Loop Gain
HTI to HTO-, f = 100 Hz,
VHTI = 20 mV
AVCLH Closed Loop Gain
HTO- to HTO+
VHT-H HTO- High Voltage
IOUT=-5.0 mA, VHTI=VB -1.0 V
VHT-L HTO- Low Voltage
IOUT=5.0 mA, VHTI=VB +1.5 V
VHT+H HTO+ High Voltage
IOUT=-5.0 mA,VHTI=VB +1.5 V
VHT+L HTO+ Low Voltage
IOUT=5.0 mA, VHTI=VB -1.0 V
LEVEL DETECTORS AND BACKGROUND NOISE MONITORS
ITH* Transmit-Recieve Switching Ratio of Current at RLI1 + RLI2 to
Threshold
20 µA at TLI1 + TLI2 to switch
from Tx to Rx
VB - 37
57
-2.8
2.8
-
2.8
-
0.8
VB +37
-
2.2
-
375
-
562
1.2
mV
dB
dB
V
mV
V
mV
FILTER
FOVOS
IFO
Voltage Offset at FO
FO Sink Current
VFO -VB, 220 KΩ from VB to FI
VB = VFO, VFI = 0 V
VB-250
112
VB +25
500
mV
µA
Note. 1. All currents into a device pin are positive, those out of a pin are negative. Algebraic convention rather
than magnitude is used to define limits.
* @25°C
SLS
System Logic
Semiconductor
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet SL34118.PDF ] | |
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