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PDF HY57V641620HGT-8 Data sheet ( Hoja de datos )
| Número de pieza | HY57V641620HGT-8 | |
| Descripción | 4 Banks x 1M x 16Bit Synchronous DRAM | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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HY57V641620HG
4 Banks x 1M x 16Bit Synchronous DRAM
D E S C R IP T IO N
The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY57V641620HG is organized as 4banks of 1,048,576x16.
HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
• Single 3.3±0 . 3 V p o w e r s u p p l y N o t e )
• All device pins are compatible with LVTTL interface
• JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
• All inputs and outputs referenced to positive edge of
system clock
• Data mask function by UDQM or LDQM
• Auto refresh and self refresh
• 4096 refresh cycles / 64ms
• Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
• Programmable CAS Latency ; 2, 3 Clocks
• Internal four banks operation
O R D E R IN G IN F O R M A T IO N
Part No.
HY57V641620HGT-5/55/6/7
HY57V641620HGT-K
HY57V641620HGT-H
HY57V641620HGT-8
HY57V641620HGT-P
HY57V641620HGT-S
HY57V641620HGLT-5/55/6/7
HY57V641620HGLT-K
HY57V641620HGLT-H
HY57V641620HGLT-8
HY57V641620HGLT-P
HY57V641620HGLT-S
C lock Frequency
200/183/166/143MHz
133MHz
133MHz
125MHz
100MHz
100MHz
200/183/166/143MHz
133MHz
133MHz
125MHz
100MHz
100MHz
Power
Normal
Low power
Organization
4Banks x 1Mbits
x16
Interface
Package
LVTTL
400mil 54pin TSOP II
N o t e : V D D ( M in ) o f H Y 5 7 V 6 4 1 6 2 0 H G ( L ) T - 5 /5 5 / 6 i s 3 . 1 3 5 V
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 0.5/Jun.01
1 page  
C A P A C IT A N C E ( T A = 2 5°C , f = 1 M H z )
Parameter
Input capacitance
Data input / output capacitance
P in
CLK
A0 ~ A11, BA0, BA1, CKE, C S, RAS,
CAS, W E, UDQM, LDQM
DQ0 ~ DQ15
O U T P U T L O A D C IR C U IT
Symbol
C I1
CI 2
M in
2
2.5
C I/O
2
HY57V641620HG
Max
4
5
6.5
Unit
pF
pF
pF
Output
V t t= 1 . 4 V
RT=250 Ω
Output
50pF
50 pF
DC Output Load Circuit
AC Output Load Circuit
D C C H A R A C T E R IS T IC S I ( T A = 0 t o 7 0 ° C , V DD = 3 . 3 ± 0 . 3 V Note3)
Param e ter
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Symbol
ILI
IL O
VOH
VOL
M in.
-1
-1
2.4
-
N o te :
1 . V I N = 0 t o 3 . 6 V , A l l o t h e r p i n s a r e n o t t e s t e d u n d e r V IN = 0 V
2.DOUT is disabled, V OUT=0 to 3.6
Max
1
1
-
0.4
Unit
uA
uA
V
V
Note
1
2
IO H = - 4 m A
IOL = + 4 m A
Rev. 0.5/Jun.01
5
5 Page 
COMMAND TRUTH TABLE
HY57V641620HG
Command
A10/
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
ADDR
BA
AP
Mode Register Set
No Operation
Bank Active
Read
Read with Autoprecharge
Write
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Burst Stop
DQM
Auto Refresh
Self Refresh1
Entry
Exit
H
H
H
H
H
H
H
H
H
H
L
Precharge
power down
Entry
Exit
H
L
Clock
Suspend
Entry
Exit
H
L
X L LL LX
OP code
HX XX
XX
L HH H
X
X L LHHX
RA
V
L
X L H L H X CA
H
V
L
X L H L L X CA
H
V
HX
X L LH L X X
LV
X L HH L X
X
X VX
H L LLHX
X
L L LLHX
HX XX
HX
L HH H
X
HX XX
LX
L HH H
HX XX
HX
L HH H
X
HX XX
LX
L V VV
X
H XX
Note
N o te :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2 . X = D o n′t c a r e , H = L o g i c H i g h , L = L o g i c L o w . B A = B a n k A d d r e s s , R A = R o w A d d r e s s , C A = C o l u m n A d d r e s s ,
Opcode = Operand Code, NOP = No Operation
Rev. 0.5/Jun.01
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet HY57V641620HGT-8.PDF ] | |
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