PDF CY7C4255 Data sheet ( Hoja de datos )

Número de pieza	CY7C4255
Descripción	8K/16Kx18 Deep Sync FIFOs
Fabricantes	Cypress Semiconductor
Logotipo
Hay una vista previa y un enlace de descarga de CY7C4255 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas
No Preview Available ! fax id: 54131CY7C4265 PRELIMINARY CY7C4255 CY7C4265 8K/16Kx18 Deep Sync FIFOs Features • High-speed, low-power, first-in first-out (FIFO) memories • 8K x 18 (CY7C4255) • 16K x 18 (CY7C4265) • 0.5 micron CMOS for optimum speed/power • High-speed 100-MHz operation (10 ns read/write cycle times) • Low power — ICC=45 mA • Fully asynchronous and simultaneous read and write operation • Empty, Full, Half Full, and programmable Almost Empty and Almost Full status flags • TTL compatible • Retransmit function • Output Enable (OE) pins • Independent read and write enable pins • Center power and ground pins for reduced noise • Supports free-running 50% duty cycle clock inputs • Width Expansion Capability • Depth Expansion Capability • 64-pin PLCC and 64-pin TQFP • Pin-compatible density upgrade to CY7C42X5 family • Pin-compatible density upgrade to IDT72205/15/25/35/45 Functional Description The CY7C4255/65 are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to the CY7C42X5 Synchronous FIFO family. The CY7C4255/65 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and commu- nications buffering. These FIFOs have 18-bit input and output ports that are con- trolled by separate clock and enable signals. The input port is controlled by a free-running clock (WCLK) and a write enable pin (WEN). When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continu- ally written into the FIFO on each cycle. The output port is controlled in a similar manner by a free-running read clock (RCLK) and a read enable pin (REN). In addition, the CY7C4255/65 have an output enable pin (OE). The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable. Retransmit and Synchronous Almost Full/Almost Empty flag features are available on these devices. Depth expansion is possible using the cascade input (WXI, RXI), cascade output (WXO, RXO), and First Load (FL) pins. The WXO and RXO pins are connected to the WXI and RXI pins of the next device, and the WXO and RXO pins of the last device should be connected to the WXI and RXI pins of the first device. The FL pin of the first device is tied to VSS and the FL pin of all the remaining devic- es should be tied to VCC. Logic Block Diagram D0 – 17 INPUT REGISTER WCLK WEN WRITE CONTROL WRITE POINTER RAM ARRAY 8K x 18 16K x 18 FLAG PROGRAM REGISTER FLAG LOGIC READ POINTER FF EF PAE PAF SMODE RS FL/RT WXI WXO/HF RXI RXO RESET LOGIC EXPANSION LOGIC THREE–STATE OUTPUT REGISTER Q0 – 17 OE READ CONTROL RCLK REN 4255–1 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 July 1995 – Revised November 1996 1 page PRELIMINARY CY7C4255 CY7C4265 AC Test Loads and Waveforms[9, 10] 5V OUTPUT R1 1.1KΩ CL INCLUDING JIG AND SCOPE R2 680Ω 4255–4 3.0V GND ≤ 3 ns ALL INPUT PULSES 90% 10% 90% 10% ≤ 3 ns Equivalent to: THÉVENIN EQUIVALENT 410Ω OUTPUT 1.91V 4255–5 Switching Characteristics Over the Operating Range 7C42X5–10 7C42X5–15 7C42X5–25 7C42X5–35 Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit tS Clock Cycle Frequency 100 66.7 40 28.6 MHz tA Data Access Time 2 8 2 10 2 15 2 20 ns tCLK Clock Cycle Time 10 15 25 35 ns tCLKH Clock HIGH Time 4.5 6 10 14 ns tCLKL Clock LOW Time 4.5 6 10 14 ns tDS Data Set-Up Time 3 4 6 7 ns tDH Data Hold Time 0.5 1 1 2 ns tENS Enable Set-Up Time 3 4 6 7 ns tENH tRS Enable Hold Time Reset Pulse Width[11] 0.5 1 1 2 ns 10 15 25 35 ns tRSR Reset Recovery Time 8 10 15 20 ns tRSF Reset to Flag and Output Time 10 15 25 35 ns tPRT Retransmit Pulse Width 30 35 45 55 ns tRTR tOLZ Retransmit Recovery Time Output Enable to Output in Low Z[12] 60 65 75 85 ns 0 0 0 0 ns tOE tOHZ Output Enable to Output Valid Output Enable to Output in High Z[12] 3 7 3 8 3 12 3 15 ns 3 7 3 8 3 12 3 15 ns tWFF Write Clock to Full Flag 8 10 15 20 ns tREF tPAFasynch Read Clock to Empty Flag Clock to Programmable Almost-Full Flag[13] (Asynchronous mode, VCC/SMODE tied to VCC) 8 10 15 20 ns 12 16 20 25 ns tPAFsynch Clock to Programmable Almost-Full Flag (Synchronous mode, VCC/SMODE tied to VSS) 8 10 15 20 ns tPAEasynch Clock to Programmable Almost-Empty Flag[13] 12 16 20 25 ns (Asynchronous mode, VCC/SMODE tied to VCC) Notes: 9. CL = 30 pF for all AC parameters except for tOHZ. 10. CL = 5 pF for tOHZ. 11. Pulse widths less than minimum values are not allowed. 12. Values guaranteed by design, not currently tested. 13. tPAFasynch, tPAEasynch, after program register write will not be valid until 5 ns + tPAF(E). 5 5 Page PRELIMINARY Switching Waveforms (continued) Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW)) tCLKH tCLKL WCLK WEN tENS tENH CY7C4255 CY7C4265 WEN2 PAE RCLK REN tENS tENH tSKEW3 [22] Note 21 tPAE synch N + 1 WORDS INFIFO tENS tENS tENH Programmable Almost Full Flag Timing Note 23 tPAE synch 4255–14 WCLK WEN tCLKH Note 24 tCLKL tENS tENH PAF [25] RCLK REN tPAF FULL– M WORDS INFIFO [26] tPAF FULL– IN(MF+IF1O) W[2O7]RDS tENS 4255–15 Notes: 21. PAE offset − n. 22. tSKEW3 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK. 23. If a read is preformed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW. 24. PAF offset = m. Number of data words written into FIFO already = 8192 − (m + 1) for the CY7C4255 and 16384 − (m + 1) for the CY7C4265. 25. PAF is offset = m. 26. 8192 − m words in CY7C4255 and 16384 - m words in CY7C4265. 27. 8192 − (m + 1) words in CY7C4255 and 16384 - (m + 1) CY7C4265. 11 11 Page

Páginas	Total 20 Páginas
PDF Descargar	[ Datasheet CY7C4255.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
CY7C425	256/512/1K/2K/4K x 9 Asynchronous FIFO	Cypress Semiconductor
CY7C425-10AC	256/512/1K/2K/4K x 9 Asynchronous FIFO	Cypress Semiconductor
CY7C425-10JC	256/512/1K/2K/4K x 9 Asynchronous FIFO	Cypress Semiconductor
CY7C425-10PC	256/512/1K/2K/4K x 9 Asynchronous FIFO	Cypress Semiconductor

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar