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PDF LTC1657IGN Data sheet ( Hoja de datos )
| Número de pieza | LTC1657IGN | |
| Descripción | Parallel 16-Bit Rail-to-Rail Micropower DAC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC1657
Parallel 16-Bit Rail-to-Rail
Micropower DAC
FEATURES
s 16-Bit Monotonic Over Temperature
s Deglitched Rail-to-Rail Voltage Output: 8nV•s
s 5V Single Supply Operation
s ICC: 650µA Typ
s Maximum DNL Error: ±1LSB
s Settling Time: 20µs to ±1LSB
s Internal or External Reference
s Internal Power-On Reset to Zero Volts
s Asynchronous CLR Pin
s Output Buffer Configurable for Gain of 1 or 2
s Parallel 16-Bit or 2-Byte Double Buffered Interface
s Narrow 28-Lead SSOP Package
s Multiplying Capability
U
APPLICATIO S
s Instrumentation
s Digital Calibration
s Industrial Process Control
s Automatic Test Equipment
s Communication Test Equipment
DESCRIPTIO
The LTC®1657 is a complete single supply, rail-to-rail
voltage output, 16-bit digital-to-analog converter (DAC) in
a 28-pin SSOP or PDIP package. It includes a rail-to-rail
output buffer amplifier, an internal 2.048V reference and
a double buffered parallel digital interface.
The LTC1657 operates from a 4.5V to 5.5V supply. It has
a separate reference input pin that can be driven by an
external reference. The full-scale output can be 1 or 2
times the reference voltage depending on how the X1/X2
pin is connected.
The LTC1657 is similar to Linear Technology Corporation’s
LTC1450 12-bit VOUT DAC family allowing an upgrade
path. It is the only buffered 16-bit parallel DAC in a 28-lead
SSOP package and includes an onboard reference for
stand alone performance.
, LTC and LT are registered trademarks of Linear Technology Corporation.
BLOCK DIAGRA
DATA IN FROM
MICROPROCESSOR
DATA BUS
FROM
MICROPROCESSOR
DECODE LOGIC
FROM
SYSTEM RESET
19 D15 (MSB)
18
17
16
15
14
13
12
D8
11 D7
10
9
8
7
6
5
4 D0 (LSB)
3 CSMSB
1 WR
2 CSLSB
28 LDAC
27 CLR
MSB
8-BIT
INPUT
REGISTER
LSB
8-BIT
INPUT
REGISTER
16-BIT
DAC
REGISTER
POWER-ON
RESET
23
REFOUT
REFERENCE
2.048V
22
REFHI
5V
24
VCC
16-BIT
DAC
+
–
R
R
GND
20
REFLO X1/X2
21 26
VOUT 25 0V TO
4.096V
1657 TA01
Differential Nonlinearity
vs Input Code
1.0
0.8
0.6
0.4
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
16384 32768 49152
DIGITAL INPUT CODE
65535
1657 G01
1
1 page  
LTC1657
PIN FUNCTIONS
WR (Pin 1): Write Input (Active Low). Used with CSMSB
and/or CSLSB to control the input registers. While WR and
CSMSB and/or CSLSB are held low, data writes into the
input register.
CSLSB (Pin 2): Chip Select Least Significant Byte (Active
Low). Used with WR to control the LSB 8-bit input regis-
ters. While WR and CSLSB are held low, the LSB byte
writes into the LSB input register. Can be connected to
CSMSB for simultaneous loading of both sets of input
latches on a 16-bit bus.
CSMSB (Pin 3): Chip Select Most Significant Byte (Active
Low). Used with WR to control the MSB 8-bit input
registers. While WR and CSMSB are held low, the MSB
byte writes into the MSB input register. Can be connected
to CSLSB for simultaneous loading of both sets of input
latches on a 16-bit bus.
D0 to D7 (Pins 4 to 11): Input data for the Least Significant
Byte. Written into LSB input register when WR = 0 and
CSLSB = 0.
D8 to D15 (Pins 12 to 19): Input data for the Most Signifi-
cant Byte. Written into MSB input register when WR = 0
and CSMSB = 0.
GND (Pin 20): Ground.
REFLO (Pin 21): Lower input terminal of the DAC’s inter-
nal resistor ladder. Typically connected to Analog Ground.
An input code of (0000)H will connect the positive input of
the output buffer to this end of the ladder. Can be used to
offset the zero scale above ground.
REFHI (Pin 22): Upper input terminal of the DAC’s internal
resistor ladder. Typically connected to REFOUT. An input
code of (FFFF)H will connect the positive input of the
output buffer to 1LSB below this voltage.
REFOUT (Pin 23): Output of the internal 2.048V reference.
Typically connected to REFHI to drive internal DAC resistor
ladder.
VCC (Pin 24): Positive Power Supply Input. 4.5V ≤ VCC ≤
5.5V. Requires a 0.1µF bypass capacitor to ground.
VOUT (Pin 25): Buffered DAC Output.
X1/X2 (Pin 26): Gain Setting Resistor Pin. Connect to GND
for G = 2 or to VOUT for G = 1. This pin should always be
tied to a low impedance source, such as ground or VOUT,
to ensure stability of the output buffer when driving
capacitive loads.
CLR (Pin 27): Clear Input (Asynchronous Active Low). A
low on this pin asynchronously resets all input and DAC
registers to 0s.
LDAC (Pin 28): Load DAC (Asynchronous Active Low).
Used to asynchronously transfer the contents of the input
registers to the DAC register which updates the output
voltage. If held low, the DAC register loads data from the
input registers which will immediately update VOUT.
5
5 Page 
LTC1657
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
GN Package
28-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.386 – 0.393*
(9.804 – 9.982)
28 27 26 25 24 23 22 21 20 19 18 17 1615
0.033
(0.838)
REF
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
0.0075 – 0.0098
(0.191 – 0.249)
0.015
(0.38
±
±
0.004
0.10)
×
45°
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1 2 3 4 5 6 7 8 9 10 11 12 13 14
0.053 – 0.069
(1.351 – 1.748)
0.004 – 0.009
(0.102 – 0.249)
0.008 – 0.012
(0.203 – 0.305)
0.0250
(0.635)
BSC
GN28 (SSOP) 1098
N Package
28-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
1.370*
(34.789)
MAX
28 27 26 25 24 23 22 21 20 19 18 17 16 15
0.255 ± 0.015*
(6.477 ± 0.381)
0.300 – 0.325
(7.620 – 8.255)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
0.130 ± 0.005
(3.302 ± 0.127)
0.045 – 0.065
(1.143 – 1.651)
0.020
(0.508)
MIN
0.009 – 0.015
(0.229 – 0.381)
+0.035
0.325 –0.015
( )8.255
+0.889
–0.381
0.125
(3.175)
MIN
0.005
(0.127)
MIN
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
0.100
(2.54)
BSC
0.018 ± 0.003
(0.457 ± 0.076)
0.065
(1.651)
TYP
N28 1098
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
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| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet LTC1657IGN.PDF ] | |
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