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PDF AM27C128 Data sheet ( Hoja de datos )
| Número de pieza | AM27C128 | |
| Descripción | 112dB 192kHz 24-BIT SCH DAC | |
| Fabricantes | Advanced Micro Devices | |
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FINAL
Am27C128
128 Kilobit (16 K x 8-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
s Fast access time
— Speed options as fast as 45 ns
s Low power consumption
— 20 µA typical CMOS standby current
s JEDEC-approved pinout
s Single +5 V power supply
s ±10% power supply tolerance standard
s 100% Flashrite™ programming
— Typical programming time of 2 seconds
s Latch-up protected to 100 mA from –1 V to
VCC + 1 V
s High noise immunity
s Versatile features for simple interfacing
— Both CMOS and TTL input/output compatibility
— Two line control functions
s Standard 28-pin DIP, PDIP, and 32-pin PLCC
packages
GENERAL DESCRIPTION
The Am27C128 is a 128-Kbit, ultraviolet erasable pro-
grammable rea d-only me mory. It is orga nized as 16
Kwords by 8 bits per word, operates from a single +5 V
supply, has a s tatic standby m ode, and features fast
single addr ess l ocation p rogramming . P roducts are
available in w indowed ceramic DIP packages, as well
as pl astic one time pr ogrammab le (O TP) P DIP and
PLCC packages.
Data can be t ypically accessed in les s than 45 ns, al-
lowing high-performance microprocessors to operate
without any WAIT s tates. Th e de vice offers separate
Output Enable (OE#) and Chip Enable (CE#) controls,
thus eliminating bus contention in a multiple bus micro-
processor system.
AMD’ s CMO S pr oc es s t echno log y pr ovides hi gh
speed, low power , an d hi gh no ise im munity. Typical
power consumption is only 80 mW in active mode, and
100 µW in standby mode.
All signals are TTL levels, including prog ramming s ig-
nals . B it loc ations ma y be pro grammed singly , in
blocks, or at r and om. The de vice s uppor ts AM D’s
Flashrite pr ogramming alg orithm (10 0 µs pulses), re-
sulting in a typical programming time of 2 seconds.
BLOCK DIAGRAM
OE#
CE#
PGM#
A0–A13
Address
Inputs
VCC
VSS
VPP
Output Enable
Chip Enable
and
Prog Logic
Y
Decoder
X
Decoder
Data Outputs
DQ0–DQ7
Output
Buffers
Y
Gating
131,072
Bit Cell
Matrix
11420E-1
Publication# 11420 Rev: E Amendment/0
Issue Date: May 1998
http://www.Datasheet4U.com
1 page  
FUNCTIONAL DESCRIPTION
Device Erasure
In order to clear all locations of their programmed con-
tents, the device must be exposed to an ultraviolet light
source. A dos age of 15 W s econds/cm2 is required to
completely erase the de vice. This dosage c an be ob-
tained by exposure to an ultraviolet lamp—wavelength
of 2537 Å—with intensity of 12,000 µW/cm2 for 15 to 20
minutes. The device should be directly under and about
one inc h from the s ource, and all fi lters should be re-
moved from the UV light source prior to erasure.
Note that all U V erasable devices will erase wit h light
sources having wavelengths shorter than 4000 Å, such
as fluorescent light and sunlight. Although the erasure
process happens over a much longer time pe riod, ex-
pos ure to an y light s ourc e should be pre vented f or
maximum system reliability. Simply cover the package
window with an opaque label or substance.
Device Programming
Upon delivery, or after each erasure, the device has all
of it s bit s in t he “ONE”, or HIGH s tate. “ZEROs” are
loaded i nto the device through t he programming p ro-
cedure.
The device enters the programming mode when 12.75
V ± 0. 25 V is appl ied t o t he V PP pin, and CE# and
PGM# are at VIL.
For p rogramming, th e dat a t o be pro grammed is ap -
plied 8 bits in parallel to the data pins.
The flo wchar t in t he Prog ramm ing s ection of t he
EPROM Pr oducts Dat a B ook (S ection 5 , Figure 5-1 )
shows AMD’s Flashrite algo rithm. The Flashrite algo-
rithm reduces programming time by using a 100 µs pro-
gramming pul se and by giv ing ea ch add ress on ly as
many pulses to reliably program the data. After each
pulse is applied to a given address, the data in that ad-
dress is verified. If the data does not verify, additional
pulses are given until it verifies or the maximum pulses
allowed is reached. This process is repeated while se-
quencing through each address of the device. This part
of the algorithm is done at VCC = 6.25 V to assure that
each EPROM bit is programmed to a s ufficiently high
threshold voltage. After the final address is completed,
the entire EPROM memory is verified at VCC = V PP =
5.25 V.
Please refer to Section 5 of the EPROM Products Data
Book for additional programming information and spec-
ifications.
Program Inhibit
Programming different data to multiple devices in par-
allel is easily accomplished. Except for CE#, all like in-
puts of the de vices may be c ommon. A T TL low-level
program pulse applied to one device’s CE# input with
VPP = 12. 75 V ± 0.25 V and P GM# LOW will program
that pa rticular device. A hi gh-level CE# in put in hibits
the other devices from being programmed.
Program Verify
A verification should be performed on the programmed
bits to determine that they were correctly programmed.
The verify should be performed with OE# and CE#, at
VIL, PGM# at VIH, and VPP between 12.5 V and 13.0 V.
Autoselect Mode
The autoselect m ode pr ovides m anufacturer an d d e-
vice i dentification th rough i dentifier cod es o n D Q0–
DQ7. This mode is primarily intended for programming
equipment t o automat ically match a de vice to be pro-
grammed w ith its c orresponding programming alg o-
rithm. This m ode is f unc tional in t he 25 °C ± 5 °C
ambient temperature range that is required when pro-
gramming the device.
To ac tivate t his mode , t he prog ramming equipment
must force VH on address line A9. Two identifier bytes
may then be sequenced from the device outputs by tog-
gling address line A0 from VIL to VIH (that is, changing
the address from 00h to 01h) . All other address lines
must be held at VIL during the autoselect mode.
Byte 0 (A 0 = V IL) re presents the man ufacturer code,
and Byte 1 (A0 = VIH), the device identifier code. Both
codes have odd parity, with DQ7 as the parity bit.
Read Mode
To obtain data at the device outputs, Chip Enable (CE#)
and Output Enable (OE#) must be driven low. CE# con-
trols the power to the device and is typically used to se-
lect the device. OE# enables the device to output data,
independent of device selection. Addresses must be
stable f or at le ast t ACC–tOE. Refer t o t he Sw itching
Waveforms section for the timing diagram.
Standby Mode
The device enters the CMOS standby mode when CE#
is at VCC ± 0.3 V. Maximum VCC current is reduced to
100 µ A. The de vice en ters t he TTL- standb y mode
when CE# is at VIH. Maximum VCC current is reduced
to 1. 0 mA . Wh en i n e ither standby mode , the d evice
places its outputs in a high-impedance state, indepen-
dent of the OE# input.
Output OR-Tieing
To ac commodate mult ipl e mem or y c onnec tions , a
two-line control function provides:
s Low memory power dissipation, and
s Assurance that output bus contention will not occur.
CE# should be dec oded and used as the primary de-
vice-selecting function, while OE# be made a common
Am27C128
5
5 Page 
PHYSICAL DIMENSIONS*
CDV028—28-Pin Ceramic Dual In-Line Package, UV Lens (measured in inches)
DATUM D
CENTER PLANE
INDEX AND
TERMINAL NO. 1
I.D. AREA
1
UV Lens
.565
.605
TOP VIEW
1.435
1.490
BASE PLANE
SEATING PLANE
.005 MIN
.045
.065
.014
.026
.015
.060
.100 BSC
SIDE VIEW
DATUM D
CENTER PLANE
.160
.220
.125
.200
.300 BSC
* For reference only. BSC is an ANSI standard for Basic Space Centering.
.700
MAX
94°
105°
.600
BSC
.008
.018
END VIEW
16-000038H-3
CDV028
DF10
3-30-95 ae
PD 028—28-Pin Plastic Dual In-Line Package (measured in inches)
1.440
1.480
28 15
.600
.625
Pin 1 I.D.
.140
.225
.045
.065
.530
.580
14
.005 MIN
.630
.700
0°
10°
.008
.015
.120
.160
.090
.110
.014
.022
.015
.060
SEATING PLANE
16-038-SB-AG
PD 028
DG75
7-13-95 ae
Am27C128
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AM27C128.PDF ] | |
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