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Número de pieza | CY62256N | |
Descripción | 256-Kbit (32 K x 8) Static RAM | |
Fabricantes | Cypress Semiconductor | |
Logotipo | ||
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256-Kbit (32 K × 8) Static RAM
256-Kbit (32 K × 8) Static RAM
Features
■ Temperature ranges
❐ Commercial: 0 °C to +70 °C
❐ Industrial: –40 °C to +85 °C
❐ Automotive-A: –40 °C to +85 °C
❐ Automotive-E: –40 °C to +125 °C
■ High speed: 55 ns
■ Voltage range: 4.5 V to 5.5 V operation
■ Low active power
❐ 275 mW (max)
■ Low standby power (LL version)
❐ 82.5 W (max)
■ Easy memory expansion with CE and OE Features
■ TTL-compatible inputs and outputs
■ Automatic power-down when deselected
■ CMOS for optimum speed and power
■ Available in Pb-free and non Pb-free 28-pin (600-mil) PDIP,
28-pin (300-mil) narrow SOIC, 28-pin TSOP I, and 28-pin
reverse TSOP I packages
Functional Description
The CY62256N is a high performance CMOS static RAM
organized as 32K words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE) and active LOW
output enable (OE) and tristate drivers. This device has an
automatic power-down feature, reducing the power consumption
by 99.9 percent when deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O0 through I/O7) is written into the memory location addressed
by the address present on the address pins (A0 through A14).
Reading the device is accomplished by selecting the device and
enabling the outputs, CE and OE active LOW, while WE remains
inactive or HIGH. Under these conditions, the contents of the
location addressed by the information on address pins are
present on the eight data input/output pins.
The input/output pins remain in a high impedance state unless
the chip is selected, outputs are enabled, and write enable (WE)
is HIGH.
For a complete list of related documentation, click here.
Logic Block Diagram
A10
A9
A8
AAA765
A4
A3
A2
CE
WE
OE
INPUTBUFFER
32K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-06511 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 16, 2015
1 page CY62256N
Capacitance
Parameter [5]
Description
CIN
COUT
Input capacitance
Output capacitance
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 5.0 V
Max Unit
6 pF
8 pF
Thermal Resistance
Parameter [5]
Description
Test Conditions
JA Thermal resistance Still air, soldered on
(junction to ambient) a 4.25 × 1.125 inch,
JC
Thermal resistance
(junction to case)
4-layer printed
circuit board
DIP
75.61
43.12
SOIC
76.56
36.07
TSOP
93.89
24.64
RTSOP
93.89
24.64
Unit
C/W
C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
5V
OUTPUT
R1 1800
5V
OUTPUT
100 pF
INCLUDING
JIG AND
SCOPE
R2
990
(a)
5 pF
INCLUDING
JIG AND
SCOPE
R1 1800
R2
990
(b)
3.0 V
GND
10%
5 ns
ALL INPUT PULSES
90%
90%
10%
< 5 ns
Equivalent to:
THÉVENIN EQUIVALENT
OUTPUT
639
1.77 V
Note
5. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-06511 Rev. *I
Page 5 of 17
5 Page CY62256N
Typical DC and AC Characteristics (continued)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
3.0
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
30.0
2.5 25.0
2.0 20.0
1.5 15.0
1.0
0.5
0.0
0.0
1.0 2.0 3.0 4.0 5.0
SUPPLY VOLTAGE (V)
10.0
5.0
VCC = 4.5 V
TA = 25 C
0.0
0
200 400 600 800 1000
CAPACITANCE (pF)
NORMALIZED ICC vs. CYCLE TIME
1.25
1.00
VCC = 5.0 V
TA = 25 C
VIN = 5.0 V
0.75
0.50
10
20 30 40
CYCLE FREQUENCY (MHz)
Truth Table
CE WE
HX
LH
LL
LH
OE Inputs/Outputs
X High Z
L Data Out
X Data In
H High Z
Mode
Deselect/power-down
Read
Write
Output Disabled
Power
Standby (ISB)
Active (ICC)
Active (ICC)
Active (ICC)
Document Number: 001-06511 Rev. *I
Page 11 of 17
11 Page |
Páginas | Total 17 Páginas | |
PDF Descargar | [ Datasheet CY62256N.PDF ] |
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