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PDF SST25PF080B Data sheet ( Hoja de datos )
| Número de pieza | SST25PF080B | |
| Descripción | 8Mbit 2.3-3.6V SPI Serial Flash | |
| Fabricantes | Microchip | |
| Logotipo |  |
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Obsolete Device
Please use SST25VF080B
SST25PF080B
8 Mbit 2.3-3.6V SPI Serial Flash
Features
• Single Voltage Read and Write Operations
- 2.3-3.6V
• Serial Interface Architecture
- SPI Compatible: Mode 0 and Mode 3
• High Speed Clock Frequency
- 80 MHz (2.7-3.6V)
- 50 MHz (2.3-2.7V)
• Superior Reliability
- Endurance: 100,000 Cycles (typical)
- Greater than 100 years Data Retention
• Low Power Consumption:
- Active Read Current: 10 mA (typical)
- Standby Current: 5 μA (typical)
• Flexible Erase Capability
- Uniform 4 KByte sectors
- Uniform 32 KByte overlay blocks
- Uniform 64 KByte overlay blocks
• Fast Erase and Byte-Program:
- Chip-Erase Time: 35 ms (typical)
- Sector-/Block-Erase Time: 18 ms (typical)
- Byte-Program Time: 7 μs (typical)
• Auto Address Increment (AAI) Programming
- Decrease total chip programming time over
Byte-Program operations
• End-of-Write Detection
- Software polling the BUSY bit in Status Register
- Busy Status readout on SO pin in AAI Mode
• Hold Pin (HOLD#)
- Suspends a serial sequence to the memory
without deselecting the device
• Write Protection (WP#)
- Enables/Disables the Lock-Down function of the
status register
• Software Write Protection
- Write protection through Block-Protection bits in
status register
• Temperature Range
- Commercial: 0°C to +70°C
• Packages Available
- 8-lead SOIC (150 mils)
- 8-lead SOIC (200 mils)
- 8-contact WSON (6mm x 5mm)
• All devices are RoHS compliant
Product Description
The 25 series Serial Flash family features a four-wire,
SPI-compatible interface that allows for a low pin-count
package which occupies less board space and ulti-
mately lowers total system costs. The SST25PF080B
devices are enhanced with improved operating fre-
quency and lower power consumption. SST25PF080B
SPI serial flash memories are manufactured with pro-
prietary, high-performance CMOS SuperFlash technol-
ogy. The split-gate cell design and thick-oxide tunneling
injector attain better reliability and manufacturability
compared with alternate approaches.
The SST25PF080B devices significantly improve per-
formance and reliability, while lowering power con-
sumption. The devices write (Program or Erase) with a
single power supply of 2.3-3.6V for SST25PF080B.
The total energy consumed is a function of the applied
voltage, current, and time of application. Since for any
given voltage range, the SuperFlash technology uses
less current to program and has a shorter erase time,
the total energy consumed during any Erase or Pro-
gram operation is less than alternative flash memory
technologies.
The SST25PF080B device is offered in 8-lead SOIC
(150 mils), 8-lead SOIC (200 mils), and 8-contact
WSON (6mm x 5mm). See Figure 2-1 for pin assign-
ments.
2014 Microchip Technology Inc.
DS20005137B-page 1
1 page  
SST25PF080B
4.2 Write Protection
SST25PF080B provides software Write protection. The
Write Protect pin (WP#) enables or disables the lock-
down function of the status register. The Block-Protec-
tion bits (BP2, BP1, BP0, and BPL) in the status regis-
ter provide Write protection to the memory array and
the status register. See Table 4-3 for the Block-Protec-
tion description.
4.2.1 WRITE PROTECT PIN (WP#)
The Write Protect (WP#) pin enables the lock-down
function of the BPL bit (bit 7) in the status register.
When WP# is driven low, the execution of the Write-
Status-Register (WRSR) instruction is determined by
the value of the BPL bit (see Table 4-1). When WP# is
high, the lock-down function of the BPL bit is disabled.
TABLE 4-1: CONDITIONS TO EXECUTE WRITE-STATUS-REGISTER (WRSR) INSTRUCTION
WP#
L
L
H
BPL
1
0
X
Execute WRSR Instruction
Not Allowed
Allowed
Allowed
4.3 Security ID
SST25PF080B offers a 256-bit Security ID (Sec ID)
feature. The Security ID space is divided into two parts
– one factory-programmed, 64-bit segment and one
user-programmable 192-bit segment. The factory-pro-
grammed segment is programmed at Microchip with a
unique number and cannot be changed. The user-pro-
grammable segment is left unprogrammed for the cus-
tomer to program as desired.
Use the Program SID command to program the Secu-
rity ID using the address shown in Table 4-5. Once pro-
grammed, the Security ID can be locked using the
Lockout SID command. This prevents any future write
to the Security ID.
The factory-programmed portion of the Security ID can
never be programmed, and none of the Security ID can
be erased.
4.4 Status Register
The software status register provides status on
whether the flash memory array is available for any
Read or Write operation, whether the device is Write
enabled, and the state of the Memory Write protection.
During an internal Erase or Program operation, the sta-
tus register may be read only to determine the comple-
tion of an operation in progress. Table 4-2 describes
the function of each bit in the software status register.
TABLE 4-2: SOFTWARE STATUS REGISTER
Bit Name
0 BUSY
1 WEL
2 BP0
3 BP1
4 BP2
5 SEC1
6 AAI
7 BPL
Function
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
Indicates current level of block write protection
Indicates current level of block write protection
Indicates current level of block write protection
Security ID status
1 = Security ID space locked
0 = Security ID space not locked
Auto Address Increment Programming status
1 = AII programming mode
0 = Byte-Program mode
1 = BP2, BP1, BP0 are read-only bits
0 = BP2, BP1, BP0 are readable/writable
Default at
Power-up
0
Read/Write
R
0R
1
1
1
0 or 1
R/W
R/W
R/W
R
0R
0 R/W
1. The Security ID status will always be ‘1’ at power-up after a successful execution of the Lockout SID instruction; otherwise,
the default at power-up is ‘0’.
2014 Microchip Technology Inc.
DS20005137B-page 5
5 Page 
SST25PF080B
CE#
MODE 3 0
SCK MODE 0
7
SI EBSY
07
WREN
0 7 8 15 16 23 24 31 32 39 40 47
AD A A A D0 D1
Load AAI command, Address, 2 bytes data
0 7 8 15 16 23
AD D2 D3
SO
CE# cont.
Check for Flash Busy Status to load next valid1 command
SCK cont.
0 7 8 15 16 23
07
07
0 7 8 15
SI cont.
AD Dn-1 Dn
WRDI
DBSY
Last 2
Data Bytes
WRDI followed by DBSY
to exit AAI Mode
SO cont.
Check for Flash Busy Status to load next valid1 command
RDSR
DOUT
Note: 1. Valid commands during AAI programming: AAI command or WRDI command
2. User must configure the SO pin to output Flash Busy status during AAI programming
25137 AAI.HW.3
FIGURE 4-8:
AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH
HARDWARE END-OF-WRITE DETECTION
Wait TBP or poll Software Status
register to load next valid1 command
CE#
MODE 3 0 7 8 15 16 23 24 31 32 39 40 47
SCK MODE 0
0 7 8 15 16 23
0 7 8 15 16 23
07
0 7 8 15
SI
AD A
A A D0 D1
AD D2 D3
AD Dn-1 Dn
WRDI
RDSR
Load AAI command, Address, 2 bytes data
SO
Last 2
Data Bytes
WRDI to exit
AAI Mode
DOUT
Note: 1. Valid commands during AAI programming: AAI command, RDSR command, or WRDI command
25137 AAI.SW.3
FIGURE 4-9:
AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH
SOFTWARE END-OF-WRITE DETECTION
2014 Microchip Technology Inc.
DS20005137B-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SST25PF080B.PDF ] | |
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