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PDF MAX4889A Data sheet ( Hoja de datos )

Número de pieza MAX4889A
Descripción 5.0Gbps PCI Express Passive Switches
Fabricantes Maxim Integrated 
Logotipo Maxim Integrated Logotipo



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No Preview Available ! MAX4889A Hoja de datos, Descripción, Manual

19-0770; Rev 2; 5/09
EVAALVUAAILTAIOBNLEKIT 5.0Gbps PCI Express Passive Switches
General Description
The MAX4888A/MAX4889A high-speed passive switches
route PCI Express® (PCIe) data between two possible
destinations. The MAX4888A is a quad single-pole/dou-
ble-throw (4 x SPDT) switch ideally suited for switching
two half lanes of PCIe data between two destinations. The
MAX4889A is an octal single-pole/double-throw (8 x
SPDT) switch ideal for switching four half lanes of PCIe
data between four destinations. The MAX4888A/
MAX4889A feature a single digital control input (SEL) to
switch signal paths.
The MAX4888A/MAX4889A are fully specified to oper-
ate from a single +3.0V to +3.6V power supply††. The
MAX4888A is available in a 3.5mm x 5.5mm, 28-pin
TQFN package. The MAX4889A is available in a 3.5mm
x 9.0mm, 42-pin TQFN package. Both devices operate
over the -40°C to +85°C temperature range.
Features
Single +3.0V to +3.6V Power-Supply Voltage
Low Same-Pair Skew of 7ps
Low 120µA (Max) Quiescent Current
Supports PCIe Gen I and Gen || Data Rates
Flow-Through Pin Configuration for Ease of
Layout
Industry-Compatible Pinout
Lead-Free Packaging
Applications
Desktop Computers
Servers/Storage Area Networks
Laptops
PART
TEMP RANGE
MAX4888AETI+
-40°C to +85°C
MAX4889AETO+
-40°C to +85°C
+Denotes lead(Pb)-free/RoHS-compliant package.
*EP = Exposed paddle.
††Contact factory if operating at +2.5V or +1.8V.
PCI Express is a registered trademark of PCI-SIG Corp.
Ordering Information/Selector Guide
PIN-PACKAGE
28 TQFN-EP*
42 TQFN-EP*
CONFIGURATION
Two Half Lanes
Four Half Lanes
Typical Application Circuit appears at end of data sheet.
Pin Configurations
TOP VIEW
24 23 22 21 20 19 18 17 16 15
GND 25
V+ 26
GND 27
V+ 28
*EP
+
MAX4888A
14 GND
13 V+
12 GND
11 V+
1 2 3 4 5 6 7 8 9 10
38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
GND 39
V+ 40
GND 41
V+ 42 *EP
+
MAX4889A
21 GND
20 V+
19 GND
18 V+
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
TQFN
*CONNECT EXPOSED PADDLE TO GROUND.
TQFN
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

1 page




MAX4889A pdf
5.0Gbps PCI Express Passive Switches
(TA = +25°C, unless otherwise noted.)
EYE DIAGRAM
(V+ = +1.8V, f = 1.25GHz,
600mVP-P PRBS SIGNAL, RS = RL = 50Ω)
VCOM_+
Typical Operating Characteristics (continued)
EYE DIAGRAM
(V+ = +2.5V, f = 1.25GHz,
600mVP-P PRBS SIGNAL, RS = RL = 50Ω)
VCOM_+
EYE DIAGRAM
(V+ = +3.3V, f = 1.25GHz,
600mVP-P PRBS SIGNAL, RS = RL = 50Ω)
VCOM_+
50mV/div
50mV/div
50mV/div
VCOM_-
50ps/div
*PRBS = PSEUDORANDOM BIT SEQUENCE
= GEN 1, 2.5Gbps; U1 = 400ps
VCOM_-
50ps/div
*PRBS = PSEUDORANDOM BIT SEQUENCE
= GEN 1, 2.5Gbps; U1 = 400ps
VCOM_-
50ps/div
*PRBS = PSEUDORANDOM BIT SEQUENCE
= GEN 1, 2.5Gbps; U1 = 400ps
EYE DIAGRAM
(V+ = +1.8V, f = 2.5GHz,
600mVP-P PRBS SIGNAL, RS = RL = 50Ω)††
VCOM_+
EYE DIAGRAM
(V+ = +2.5V, f = 2.5GHz,
600mVP-P PRBS SIGNAL, RS = RL = 50Ω)††
VCOM_+
EYE DIAGRAM
(V+ = +3.3V, f = 2.5GHz,
600mVP-P PRBS SIGNAL, RS = RL = 50Ω)††
VCOM_+
50mV/div
50mV/div
50mV/div
VCOM_-
25ps/div
*PRBS = PSEUDORANDOM BIT SEQUENCE
†† = GEN 11, 5.0Gbps; U1 = 200ps
VCOM_-
25ps/div
*PRBS = PSEUDORANDOM BIT SEQUENCE
†† = GEN 11, 5.0Gbps; U1 = 200ps
VCOM_-
25ps/div
*PRBS = PSEUDORANDOM BIT SEQUENCE
†† = GEN 11, 5.0Gbps; U1 = 200ps
_______________________________________________________________________________________ 5

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MAX4889A arduino
5.0Gbps PCI Express Passive Switches
Applications Information
PCIe Switching
The MAX4888A/MAX4889A primary applications are
aimed at reallocating PCIe lanes (see Figure 5). For
example, in graphics applications, several manufacturers
have found that it is possible to improve performance by
a factor of nearly two by splitting a single 16-lane PCIe
bus into two 8-lane buses. Two of the more prominent
examples are SLI™ (Scaled Link Interface) and
CrossFire™. The MAX4889A permits a computer
motherboard to operate properly with a single 16-lane
graphics card, and can later be updated to dual cards.
The same motherboard can be used with dual cards
where the user sets a jumper or a bit through software
to switch between single- or dual-card operation.
Common mode below 1V operation requirement.
Board Layout
High-speed switches require proper layout and design
procedures for optimum performance. Keep design-
controlled impedance PCB traces as short as possible
or follow impedance layouts per the PCIe specification.
Ensure that power-supply bypass capacitors are
placed as close to the device as possible. Multiple
bypass capacitors are recommended. Connect all
grounds and the exposed pad to large ground planes.
Common mode below 1V operation requirement.
ONE LANE
MAX4888A
MAX4889A
DATA
DIRECTION
ESD Protection
As with all Maxim devices, ESD-protection structures
are incorporated on all pins to protect against electro-
static discharges encountered during handling and
assembly. The COM_+ and COM_- lines have extra
protection against static electricity. Maxim’s engineers
have developed state-of-the-art structures to protect
these pins against ESD of ±6kV without damage. The
ESD structures withstand ±6kV of ESD in all states: nor-
mal operation, state output mode, and powered down.
Human Body Model
The MAX4889A COM_+ and COM_- pins are character-
ized for ±6kV ESD protection using the Human Body
Model (MIL-STD-883, Method 3015). Figure 6 shows
the Human Body Model and Figure 7 shows the current
waveform it generates when discharged into low
impedance. This model consists of a 100pF capacitor
charged to the ESD voltage of interest, which is then
discharged into the device through a resistor.
RC
1MΩ
RD
1500Ω
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
SOURCE
Cs
100pF
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
Figure 6. Human Body ESD Test Model
NOTE: ONLY ONE LANE IS SHOWN FOR CLARITY
DATA IS ROUTED
TO EITHER
BOARD A OR B
AB
Figure 5. The MAX4888A/MAX4889A Used as a Single-Lane
Switch
CrossFire is a trademark of ATI Technologies, Inc.
SLI is a trademark of NVIDIA Corporation.
IP 100%
90%
Ir PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
AMPERES
36.8%
10%
0
0
tRL
TIME
tDL
CURRENT WAVEFORM
Figure 7. Human Body Model Current Waveform
PROCESS: CMOS
Chip Information
______________________________________________________________________________________ 11

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