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PDF MAX2880 Data sheet ( Hoja de datos )
| Número de pieza | MAX2880 | |
| Descripción | Fractional/Integer-N PLL | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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MAX2880
EVALUATION KIT AVAILABLE
250MHz to 12.4GHz, High-Performance,
Fractional/Integer-N PLL
General Description
The MAX2880 is a high-performance phase-locked
loop (PLL) capable of operating in both integer-N and
fractional-N modes. Combined with an external reference
oscillator, loop filter, and VCO, the device forms an ultra-
low noise and low-spur frequency synthesizer capable of
accepting RF input frequencies of up to 12.4GHz.
The MAX2880 consists of a high-frequency and low-
noise-phase frequency detector (PFD), precision charge
pump, 10-bit programmable reference counter, 16-bit
integer N counter, and 12-bit variable modulus fractional
modulator.
The MAX2880 is controlled by a 3-wire serial interface
and is compatible with 1.8V control logic. The device is
available in a lead-free, RoHS-compliant, 20-pin TQFN
and 16-pin TSSOP packages, and operates over an
extended -40°C to +85°C temperature range.
Applications
●● Microwave Point-to-Point Systems
●● Wireless Infrastructure
●● Satellite Communications
●● Test and Measurement
●● RF DAC and ADC Clocks
Functional Diagram
Benefits and Features
●● Integer and Fractional-N Modes
●● 250MHz to 12.4GHz Broadband RF Input
●● Normalized In-Band Noise Floor
• -229dBc/Hz in Integer Mode
• -227dBc/Hz in Fractional Mode
●● -10dBm to +5dBm Wide Input Sensitivity
●● Low-Noise Phase Frequency Detector
• 125MHz in Fractional Mode
• 140MHz in Integer Mode
●● Reference Frequency Up to 210MHz
●● Operates from +2.8V to +3.6V Supply
●● Cycle Slip Reduction and Fast Lock
●● Software and Hardware Shutdown
●● Software Lock Detect
●● On-Chip Temperature Sensor
●● Compatible with +1.8V Control Logic
●● Phase Adjustment
Ordering Information appears at end of data sheet.
VCP
REF REF
DIV
x2 ÷ 2
DAT
LE SPI AND REGISTERS
CLK
12-BIT
FRAC
12-BIT
MOD
16-BIT
INT
PROGRAMMABLE MAIN
MODULATOR
MUX I/O
+
N
COUNTER
PFD CP
CP
LD
RFINN
RFINP
÷ 2 CE
MUX
MAX2880
MUX
19-6871; Rev 1; 11/15
1 page  
MAX2880
250MHz to 12.4GHz, High-Performance,
Fractional/Integer-N PLL
Typical Operating Characteristics (continued)
(Measured using the MAX2880 Evaluation Kit. VCC_ = 3.3V, VGND_ = 0V, VCP = 5.0V, CP[3:0]= 1111, fRFINN = 6GHz, fREF = 50MHz,
fPFD = 50MHz, TA = +25°C, unless otherwise noted. See Table 1 and Table 2).
NORMALIZED 1/f NOISE vs. TEMPERATURE
-110
OFFSET = 10kHz
toc04
FRAC-N LOW SPUR
-115
-120
-125
FRAC-N LOW NOISE
INTEGER-N
-130
-40
-15 10 35
TEMPERATURE (°C)
60
85
INTEGER-N CLOSED-LOOP PHASE NOISE
vs. OFFSET FREQUENCY
-80 toc07
LBW = 50kHz
-90
-100
-110
TA = +85°C
-120
-130
-140
TA = -40°C,+25°C
-150
-160
-170
1
10 100 1000 10000 100000
fOFFSET (kHz)
NORMALIZED 1/f NOISE
vs. CP CURRENT CODE
-110
OFFSET = 10kHz
toc05
FRAC-N LOW SPUR
-115
-120
FRAC-N LOW NOISE
-125
INTEGER-N
-130
0
3 6 9 12
CP CURRENT CODE
15
FRAC-N LOW-NOISE MODE
CLOSED-LOOP PHASE NOISE
vs. OFFSET FREQUENCY
-80 toc08
LBW = 50kHz
-90
-100
-110
TA = +85°C
-120
-130
-140
TA = -40°C,+25°C
-150
-160
-170
1
10 100 1000 10000 100000
fOFFSET (kHz)
RF INPUT SENSITIVITY vs. FREQUENCY
-5 toc10
-15
-25
-35
-45
0
2468
FREQUENCY (GHz)
10 12
NORMALIZED 1/f NOISE
vs. TUNE VOLTAGE
-110
OFFSET = 10kHz
toc06
FRAC-N LOW SPUR
-115
-120
-125 FRAC-N LOW NOISE
INTEGER-N
-130
0.5 1 1.5 2 2.5 3 3.5 4
VTUNE (V)
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
1
FRAC-N LOW-SPUR MODE
CLOSED-LOOP PHASE NOISE
vs. OFFSET FREQUENCY
toc09
LBW = 50kHz
TA = +85°C
TA = -40°C,+25°C
10 100 1000 10000 100000
fOFFSET (kHz)
www.maximintegrated.com
Maxim Integrated │ 5
5 Page 
MAX2880
250MHz to 12.4GHz, High-Performance,
Fractional/Integer-N PLL
MUX and Lock Detect
MUX is a multipurpose test output for observing various
internal functions of the MAX2880. MUX can also be
configured as serial data output. MUX bits (register 0, bit
30:27) are used to select the desired MUX signal (see
Table 5).
The digital lock detect is dependent on the mode of the
synthesizer. In fractional-N mode set LDF = 0, and in
integer-N mode set LDF = 1. To set the accuracy of the
digital lock detect, see Table 3 and Table 4.
Cycle Slip Reduction
Cycle slip reduction is one of two available methods to
improve lock time. It is enabled by setting CSR bit (regis-
ter 2, bit 28) to 1. In this mode, the charge pump must be
set for its minimum value.
Fast-Lock
Fast-lock is the other method available for improving lock
time by temporarily increasing the loop bandwidth at the
start of the locking cycle. It is enabled by setting the CDM
bits to 01 (register 4, bits 20:19). In addition, the charge-
pump current has to be set to CP = 0000 (register 2,
bits 27:24), MUX bits configured to 1100 (register 0, bits
30:27), and the shunt resistive portion of the loop filter has
to be segmented into two parts, where one resistor is 1/4
of the total resistance, and the other resistor is 3/4 of the
total resistance. Figure 4 and Figure 5 illustrate the two
possible topologies. Once enabled, fast lock is activated
after writing to register 0. During this process, the charge
pump is automatically increased to its maximum (CP bits
= 1111) and the shunt loop filter resistance is reduced to
1/4 of the total resistance when the internal switch shorts
the MUX pin to ground. Bits CDIV (register 4, bits 18:7)
control the time spent in the wide bandwidth mode. The
time spent in the fast lock is:
t = CDIV/fPFD
The time should be set long enough to allow the loop to
settle before switching back to the lower loop bandwidth.
RF Inputs
The differential RF inputs are connected to a high-imped-
ance input buffer which drives a demultiplexer for select-
ing between two RF input frequency ranges: 250MHz to
6.2GHz and 6.2GHz to 12.4GHz. When the RF input fre-
quency is 250MHz to 6.2GHz, the fixed divide-by-2 pres-
caler is bypassed by setting bit PRE to 0. When the RF
input frequency is 6.2GHz to 12.4GHz, the fixed divide-
by-2 path is selected by setting PRE to 1. The supported
input power range is -10dBm to +5dBm. For single-ended
operation, terminate the unused RF input to GND through
a 100pF capacitor.
Since the RF input of the device is high impedance, a
DC isolated external shunt resistor is used to provide
the 50Ω input impedance for the system (see the Typical
Application Circuit).
Table 3. Fractional-N Digital Lock-Detect Settings
PFD FREQUENCY
(MHz)
≤ 32
≤ 32
> 32
LDS
0
0
1
LDP
0
1
X
LOCKED UP/DOWN
TIME SKEW (ns)
10
6
4
NUMBER OF LOCKED
CYCLES TO SET LD
40
40
40
TIME SKEW TO
UNSET LD (ns)
15
15
4
Table 4. Integer-N Digital Lock-Detect Settings
PFD FREQUENCY
(MHz)
≤ 32
≤ 32
> 32
LDS
0
0
1
LDP
0
1
X
LOCKED UP/DOWN
TIME SKEW (ns)
10
6
4
NUMBER OF LOCKED
CYCLES TO SET LD
5
5
5
TIME SKEW TO
UNSET LD (ns)
15
15
4
www.maximintegrated.com
Maxim Integrated │ 11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MAX2880.PDF ] | |
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