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PDF ISL5627 Data sheet ( Hoja de datos )
| Número de pieza | ISL5627 | |
| Descripción | Dual 8-bit 3.3V 260MSPS High Speed D/A Converter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
Data Sheet
May 2004
ISL5627
www.DataSheet4U.com
FN6081
Dual 8-bit, +3.3V, 260+MSPS, High Speed
D/A Converter
The ISL5627 is a dual 8-bit, 260+MSPS (Mega Samples Per
Second), CMOS, high speed, low power, D/A (digital to
analog) converter, designed specifically for use in
communication systems.
This device complements the ISL5x57 and ISL5x27 families
of high speed converters, which include 8-, 10-, 12-, and
14-bit devices.
Ordering Information
PART
NUMBER
ISL5627IN
ISL5627EVAL1
TEMP.
RANGE
(°C)
PACKAGE
PKG. CLOCK
DWG. # SPEED
-40 to 85 48 Ld LQFP Q48.7x7A 260MHz
25 Evaluation Platform
260MHz
Pinout
ISL5627
(LQFP)
TOP VIEW
Features
• Low Power . . . . . 233mW with 20mA Output at 130MSPS
• Adjustable Full Scale Output Current . . . . . 2mA to 20mA
• Guaranteed Gain Matching < 0.14dB
• +3.3V Power Supply
• 3V LVCMOS Compatible Inputs
• Excellent Spurious Free Dynamic Range
(67dBc to Nyquist, fS = 130MSPS, fOUT = 10MHz)
• Dual, 3.3V, Lower Power Replacement for AD9709
Applications
• Quadrature Transmit with IF Range 0-80MHz
• Medical/Test Instrumentation and Equipment
• Wireless Communication Systems
ID1
(LSB) ID0
NC
NC
NC
NC
NC
NC
SLEEP
DVDD
AGND
ICOMP
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28
10 27
11 26
1213 14 15 16
25
17 18 19 20 21 22 23 24
QD0 (LSB)
QD1
QD2
QD3
QD4
QD5
QD6
QD7 (MSB)
CLK
DGND
AGND
QCOMP
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL5627
Absolute Maximum Ratings
Digital Supply Voltage DVDD to DGND . . . . . . . . . . . . . . . . . . +3.6V
Analog Supply Voltage AVDD to AGND . . . . . . . . . . . . . . . . . . +3.6V
Grounds, AGND TO DGND . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (DATA, CLK, SLEEP) . . . . . . . . DVDD + 0.3V
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AVDD + 0.3V
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
Thermal Information
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Thermal Resistance (Typical, Note 1)
θJA(°C/W)
LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25°C for All Typical Values
PARAMETER
TEST CONDITIONS
TA = -40°C TO 85°C
MIN TYP MAX
UNITS
SYSTEM PERFORMANCE
Resolution
8-
- Bits
Integral Linearity Error, INL
“Best Fit” Straight Line (Note 8)
-0.5 ±0.05 +0.5
LSB
Differential Linearity Error, DNL
(Note 8)
-0.5 ±0.05 +0.5
LSB
Offset Error, IOS
Offset Drift Coefficient
IOUTA (Note 8)
(Note 8)
-0.006
+0.006 % FSR
- 0.1
- ppm
FSR/°C
Full Scale Gain Error, FSE
With External Reference (Notes 2, 8)
-3 ±0.5 +3 % FSR
With Internal Reference (Notes 2, 8)
-3 ±0.5 +3 % FSR
Full Scale Gain Drift
With External Reference (Note 8)
- ±50
- ppm
FSR/°C
With Internal Reference (Note 8)
- ±100
- ppm
FSR/°C
Crosstalk
Gain Matching Between Channels
(DC Measurement)
fCLK = 100MSPS, fOUT = 10MHz
fCLK = 100MSPS, fOUT = 40MHz
fCLK = 260MSPS, fOUT = 40.4MHz
As a percentage of Full Scale Range
In dB Full Scale Range
- 83
-
dB
- 74
-
dB
- 73
-
dB
-1.6 0.6 +1.6 % FSR
-0.14 0.05 +0.14 dB FSR
Full Scale Output Current, IFS
Output Voltage Compliance Range
(Note 3)
2 20 22
-1.0 - 1.25
mA
V
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, fCLK
Output Rise Time
Full Scale Step
260 300
-1
-
-
MHz
ns
Output Fall Time
Full Scale Step
- 1 - ns
Output Capacitance
- 5 - pF
Output Noise
IOUTFS = 20mA
- 50
- pA/√Hz
IOUTFS = 2mA
- 30
- pA/√Hz
5
5 Page 
ISL5627
REQ = 0.5 x (RLOAD//RDIFF)
AT EACH OUTPUT
ISL5627
OUTA
OUTB
RDIFF
VOUT = (2 x OUTA x REQ)V
1:1
RLOAD
RLOAD REPRESENTS THE
LOAD SEEN BY THE TRANSFORMER
FIGURE 6. OUTPUT LOADING FOR DATASHEET
MEASUREMENTS
REQ = 0.5 x (RLOAD//RDIFF//RA), WHERE RA = RB
AT EACH OUTPUT
ISL5627
OUTA
OUTB
RA
RDIFF
RB
VOUT = (2 x OUTA x REQ)V
RLOAD
Propagation Delay
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The converter requires two clock rising edges for data to be
represented at the output. Each rising edge of the clock
captures the present data word and outputs the previous
data. The propagation delay is therefore 1/CLK, plus <2ns of
processing. See Figure 8.
Test Service
Intersil offers customer-specific testing of converters with a
service called Testdrive. To submit a request, fill out the
Testdrive form at www.intersil.com/testdrive. Or, send a
request to the technical support center.
RLOAD REPRESENTS THE
LOAD SEEN BY THE TRANSFORMER
FIGURE 7. ALTERNATIVE OUTPUT LOADING
Timing Diagram
CLK
D7-D0
tPW1
tPW2
tSU
W0
tHLD
tSU
W1
tHLD
tSU
W2
tHLD
50%
W3
IOUT
tPD
OUTPUT = W-1
tPD
OUTPUT = W0
OUTPUT = W1
FIGURE 8. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ISL5627.PDF ] | |
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