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PDF LTC3568 Data sheet ( Hoja de datos )
| Número de pieza | LTC3568 | |
| Descripción | Synchronous Step-Down DC/DC Converter | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
■ Uses Tiny Capacitors and Inductor
■ High Frequency Operation: Up to 4MHz
■ Low RDS(ON) Internal Switches: 0.110Ω
■ High Efficiency: Up to 96%
■ Stable with Ceramic Capacitors
■ Current Mode Operation for Excellent Line
and Load Transient Response
■ Short-Circuit Protected
■ Low Dropout Operation: 100% Duty Cycle
■ Low Shutdown Current: IQ ≤ 1μA
■ Low Quiescent Current: 60μA
■ Output Voltages from 0.8V to 5V
■ Selectable Burst Mode® Operation
■ Sychronizable to External Clock
■ Small 3mm × 3mm, 10-Lead DFN Package
APPLICATIONS
■ Notebook Computers
■ Digital Cameras
■ Cellular Phones
■ Handheld Instruments
■ Board Mounted Power Supplies
LTC3568www.DataSheet4U.com
1.8A, 4MHz, Synchronous
Step-Down DC/DC Converter
DESCRIPTION
The LTC®3568 is a constant frequency, synchronous
step- down DC/DC converter. Intended for medium power
applications, it operates from a 2.5V to 5.5V input voltage
range and has a user configurable operating frequency
up to 4MHz, allowing the use of tiny, low cost capacitors
and inductors 2mm or less in height. The output voltage
is adjustable from 0.8V to 5V. Internal sychronous 0.11Ω
power switches with 2.4A peak current ratings provide
high efficiency. The LTC3568’s current mode architecture
and external compensation allow the transient response
to be optimized over a wide range of loads and output
capacitors.
The LTC3568 can be configured for automatic power sav-
ing Burst Mode operation to reduce gate charge losses
when the load current drops below the level required for
continuous operation. For reduced noise and RF interfer-
ence, the SYNC/MODE pin can be configured to skip pulses
or provide forced continuous operation.
To further maximize battery life, the P-channel MOSFET
is turned on continuously in dropout (100% duty cycle)
with a low quiescent current of 60μA. In shutdown, the
device draws <1μA.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Burst
Mode is a registered trademark of Linear Technology Corporation. All other trademarks are
the property of their respective owners. Protected by U.S. Patents including 5481178,
6580258, 6304066, 6127815, 6611131.
TYPICAL APPLICATION
VIN
2.5V TO 5.5V
13k
1000pF
VIN SYNC/MODE
PVIN
PGOOD
SVIN
SW
LTC3568
ITH
SHDN/RT
VFB
SGND PGND
324k
22μF
L1
2μH VOUT
2.5V/1.8A
887k
22μF + 10μF
412k
NOTE: IN DROPOUT, THE OUTPUT TRACKS
THE INPUT VOLTAGE
3568 F01
Figure 1. Step-Down 1.8A Regulator
Efficiency vs Load Current
100
1000
95
EFFICIENCY
90
100
85
POWER LOSS
80 10
VIN = 3.3V
VOUT = 2.5V
75 fO = 1MHz
Burst Mode
70 OPERATION 1
1 10 100 1000 10000
LOAD CURRENT (mA)
3568 TA01
3568f
1
1 page  
LTC3568www.DataSheet4U.com
PIN FUNCTIONS
SHDN/RT (Pin 1): Combination Shutdown and Timing
Resistor Pin. The oscillator frequency is programmed by
connecting a resistor from this pin to ground. Forcing
this pin to SVIN causes the device to be shut down. In
shutdown all functions are disabled.
SYNC/MODE (Pin 2): Combination Mode Selection and
Oscillator Synchronization Pin. This pin controls the op-
eration of the device. When tied to SVIN or SGND, Burst
Mode operation or pulse skipping mode is selected,
respectively. If this pin is held at half of SVIN, the forced
continuous mode is selected. The oscillation frequency
can be syncronized to an external oscillator applied to
this pin. When synchronized to an external clock pulse
skip mode is selected.
SGND (Pin 3): The Signal Ground Pin. All small signal
components and compensation components should be con-
nected to this ground (see Board Layout Considerations).
SW (Pin 4): The Switch Node Connection to the Inductor.
This pin swings from PVIN to PGND.
PGND (Pin 5): Main Power Ground Pin. Connect to the
(–) terminal of COUT, and (–) terminal of CIN.
PVIN (Pin 6): Main Supply Pin. Must be closely decoupled
to PGND.
SVIN (Pin 7): The Signal Power Pin. All active circuitry
is powered from this pin. Must be closely decoupled to
SGND. SVIN must be greater than or equal to PVIN.
PGOOD (Pin 8): The Power Good Pin. This common drain
logic output is pulled to SGND when the output voltage is
not within ±7.5% of regulation.
VFB (Pin 9): Receives the feedback voltage from the ex-
ternal resistive divider across the output. Nominal voltage
for this pin is 0.8V.
ITH (Pin 10): Error Amplifier Compensation Point. The cur-
rent comparator threshold increases with this control volt-
age. Nominal voltage range for this pin is 0V to 1.5V.
Exposed Pad (Pin 11): Thermal Ground. Connect to SGND
and solder to the PCB for rated thermal performance.
BLOCK DIAGRAM
SVIN
7
SGND
3
ITH
10
VFB 9
0.8V VOLTAGE
REFERENCE
+
–
0.74V +
ERROR
AMPLIFIER
VB
–
ITH
LIMIT
BCLAMP
–
+
BURST
COMPARATOR
HYSTERESIS = 80mV
OSCILLATOR
PVIN
6
PMOS CURRENT
COMPARATOR
+
–
SLOPE
COMPENSATION
4 SW
PGOOD 8
+
0.86V –
1
SHDN/RT
LOGIC
NMOS
COMPARATOR
+
–
–
REVERSE
COMPARATOR
2
SYNC/MODE
+
5 PGND
3568 BD
3568f
5
5 Page 
LTC3568www.DataSheet4U.com
APPLICATIONS INFORMATION
that will give a sense of the overall loop stability without
breaking the feedback loop.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, VOUT im-
mediately shifts by an amount equal to ΔILOAD • ESR, where
ESR is the effective series resistance of COUT. ΔILOAD also
begins to charge or discharge COUT generating a feedback
error signal used by the regulator to return VOUT to its
steady-state value. During this recovery time, VOUT can
be monitored for overshoot or ringing that would indicate
a stability problem.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second
order overshoot/DC ratio cannot be used to determine
phase margin. The gain of the loop increases with R and
the bandwidth of the loop increases with decreasing C.
If R is increased by the same factor that C is decreased,
the zero frequency will be kept the same, thereby keeping
the phase the same in the most critical frequency range
of the feedback loop. In addition, a feedforward capacitor
CF can be added to improve the high frequency response,
as shown in Figure 5. Capacitor CF provides phase lead by
creating a high frequency zero with R2 which improves
the phase margin.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Linear Technology
Application Note 76.
Although a buck regulator is capable of providing the full
output current in dropout, it should be noted that as the
input voltage VIN drops toward VOUT, the load step capability
does decrease due to the decreasing voltage across the
inductor. Applications that require large load step capabil-
ity near dropout should use a different topology such as
SEPIC, Zeta or single inductor, positive buck/boost.
In some applications, a more severe transient can be caused
by switching in loads with large (>1uF) input capacitors.
The discharged input capacitors are effectively put in paral-
lel with COUT, causing a rapid drop in VOUT. No regulator
can deliver enough current to prevent this problem, if the
switch connecting the load has low resistance and is driven
quickly. The solution is to limit the turn-on speed of the load
switch driver. A hot swap controller is designed specifically
for this purpose and usually incorporates current limiting,
short-circuit protection, and soft-starting.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
VIN
2.5V
TO 5.5V
C6
PGND
+
CIN
R6
C8
PGND
SVIN
PVIN PGOOD
SW
LTC3568
SGND
SYNC/MODE
SGND
CITH
ITH VFB
RC SGND PGND SHDN/RT
CC
R5
PGOOD
L1 CF
R1
RT
R2
SGND SGND
GND
SGND SGND
Figure 5. LTC3568 General Schematic
+
COUT
VOUT
C5
PGND
PGND
3568 F05
3568f
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet LTC3568.PDF ] | |
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