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PDF HI5808 Data sheet ( Hoja de datos )
| Número de pieza | HI5808 | |
| Descripción | 10 MSPS A/D Converter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Data Sheet
HI5808
February 1999 File Number 4233.4
12-Bit, 10 MSPS A/D Converter
The HI5808 is a monolithic, 12-bit, Analog-to-Digital
Converter fabricated in Intersil’s HBC10 BiCMOS process. It
is designed for high speed, high resolution applications
where wide bandwidth and low power consumption are
essential.
The HI5808 is designed in a fully differential pipelined
architecture with a front end differential-in-differential-out
sample-and-hold (S/H). The HI5808 has excellent dynamic
performance while consuming 325mW power at 10 MSPS.
The 100MHz full power input bandwidth is ideal for
communication systems and document scanner
applications. Data output latches are provided which present
valid data to the output bus with a latency of 3 clock cycles.
The digital outputs have a separate supply pin which can be
powered from a 3V to 5V supply.
Ordering Information
PART
SAMPLE
TEMP.
PKG.
NUMBER
RATE RANGE (oC) PACKAGE NO.
HI5808BIB 10 MSPS -40 to 85 28 Ld SOIC M28.3
HI5808EVAL1
25 Evaluation Board
Pinout
HI5808
(SOIC)
TOP VIEW
CLK 1
DVCC1 2
DGND1 3
DVCC1 4
DGND1 5
AVCC
AGND
VIN+
6
7
8
VIN- 9
VDC 10
VROUT 11
VRIN 12
AGND 13
AVCC 14
28 D0
27 D1
26 D2
25 D3
24 D4
23 D5
22 DVCC2
21 DGND2
20 D6
19 D7
18 D8
17 D9
16 D10
15 D11
Features
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 10 MSPS
• Low Power
• Internal Sample and Hold
• Fully Differential Architecture
• Full Power Input Bandwidth . . . . . . . . . . . . . . . . . 100MHz
• Low Distortion
• Internal Voltage Reference
• TTL/CMOS Compatible Digital I/O
• Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . 5V to 3.0V
Applications
• Digital Communication Systems
• Undersampling Digital IF
• Document Scanners
• Additional Reference Documents
- AN9214 Using Intersil High Speed A/D Converters
- AN9724 Using the HI5808EVAL1 Evaluation Board
117
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1 page  
Timing Waveforms
ANALOG
INPUT
HI5808
CLOCK
INPUT SN - 1 HN - 1 SN
HN SN + 1 HN + 1 SN + 2 HN + 2 SN + 3 HN + 3 SN + 4 HN + 4 SN + 5 HN + 5 SN + 6 HN + 6
INPUT
S/H
1ST
STAGE
B1, N - 1
B1, N
B1, N + 1
B1, N + 2
B1, N + 3
B1, N + 4
B1, N + 5
2ND
STAGE
3RD
STAGE
4TH
STAGE
B2, N - 2
B2, N - 1
B2, N
B2, N + 1
B2, N + 2
B2, N + 3
B2, N + 4
B3, N - 2
B3, N - 1
B3, N
B3, N + 1
B3, N + 2
B3, N + 3
B3, N + 4
B4, N - 3
B4, N - 2
B4, N - 1
B4, N
B4, N + 1
B4, N + 2
B4, N + 3
DATA
OUTPUT
DN - 3
DN - 2
DN - 1
DN
tLAT
NOTES:
4. SN: N-th sampling period.
5. HN: N-th holding period.
6. BM, N: M-th stage digital output corresponding to N-th sampled input.
7. DN: Final data output corresponding to N-th sampled input.
FIGURE 1. INTERNAL CIRCUIT TIMING
DN + 1
DN + 2
DN + 3
ANALOG
INPUT
CLOCK
INPUT
tAP
tAJ
1.5V
1.5V
tOD
tH
DATA
OUTPUT
DATA N - 1
2.0V
0.8V
DATA N
FIGURE 2. INPUT-TO-OUTPUT TIMING
121
5 Page 
HI5808
Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to
evaluate the dynamic performance of the HI5808. A low
distortion sine wave is applied to the input, it is coherently
sampled, and the output is stored in RAM. The data is then
transformed into the frequency domain with an FFT and ana-
lyzed to evaluate the dynamic performance of the A/D. The
sine wave input to the part is -0.5dB down from full scale for
all these tests. SNR and SINAD are quoted in dB. The
distortion numbers are quoted in dBc (decibels with respect
to carrier) and DO NOT include any correction factors for
normalizing to full scale.
Signal-to-Noise Ratio (SNR)
SNR is the measured RMS signal to RMS noise at a
specified input and sampling frequency. The noise is the
RMS sum of all of the spectral components except the
fundamental and the first five harmonics.
Signal-to-Noise + Distortion Ratio (SINAD)
SINAD is the measured RMS signal to RMS sum of all
other spectral components below the Nyquist frequency,
fS/2, excluding DC.
Effective Number Of Bits (ENOB)
The effective number of bits (ENOB) is calculated from the
SINAD data by:
ENOB = (SINAD + VCORR-1.76)/6.02,
where: VCORR = 0.5dB.
VCORR adjusts the ENOB for the amount the input is below
full scale.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first 5 harmonic
components to the RMS value of the fundamental input
signal.
2nd and 3rd Harmonic Distortion
This is the ratio of the RMS value of the applicable
harmonic component to the RMS value of the fundamental
input signal.
Spurious Free Dynamic Range (SFDR)
SFDR is the ratio of the fundamental RMS amplitude to the
RMS amplitude of the next largest spur or spectral compo-
nent in the spectrum below fS/2.
Intermodulation Distortion (IMD)
Nonlinearities in the signal path will tend to generate inter-
modulation products when two tones, f1 and f2, are present
at the inputs. The ratio of the measured signal to the
distortion terms is calculated. The terms included in the
calculation are (f1 + f2), (f1 - f2), (2f1), (2f2), (2f1 + f2),
(2f1 - f2), (f1 + 2f2), (f1 - 2f2). The ADC is tested with each
tone 6dB below full scale.
Transient Response
Transient response is measured by providing a full-scale
transition to the analog input of the ADC and measuring the
number of cycles it takes for the output code to settle within
12-bit accuracy.
Over-Voltage Recovery
Over-voltage Recovery is measured by providing a full-scale
transition to the analog input of the ADC which overdrives
the input by 200mV, and measuring the number of cycles it
takes for the output code to settle within 12-bit accuracy.
Full Power Input Bandwidth (FPBW)
Full power input bandwidth is the analog input frequency at
which the amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sinewave.
The input sinewave has an amplitude which swings from -fS
to +fS. The bandwidth given is measured at the specified
sampling frequency.
Timing Definitions
Refer to Figure 1, Internal Circuit Timing, and Figure 2,
Input-To-Output Timing, for these definitions.
Aperture Delay (tAP)
Aperture delay is the time delay between the external
sample command (the falling edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Jitter (tAJ)
Aperture Jitter is the RMS variation in the aperture delay due
to variation of internal clock path delays.
Data Hold Time (tH)
Data hold time is the time to where the previous data (N - 1)
is no longer valid.
Data Output Delay Time (tOD)
Data output delay time is the time to where the new data (N)
is valid.
Data Latency (tLAT)
After the analog sample is taken, the digital data is output on
the bus at the third cycle of the clock. This is due to the pipe-
line nature of the converter where the data has to ripple
through the stages. This delay is specified as the data
latency. After the data latency time, the data representing
each succeeding sample is output at the following clock
pulse. The digital data lags the analog input sample by 3
clock cycles.
127
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet HI5808.PDF ] | |
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