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PDF SPT8100 Data sheet ( Hoja de datos )
| Número de pieza | SPT8100 | |
| Descripción | 16-BIT / 5 MSPS CMOS A/D CONVERTER | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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SPT8100
16-BIT, 5 MSPS CMOS A/D CONVERTER
FEATURES
APPLICATIONS
TECHNICAL DATA
JANUARY 9, 2002
• 16-bit, 5 MSPS CMOS analog-to-digital converter
• On-chip PGA: gain range from 0 to 19.5 dB in seven
selectable settings:
0 dB, +2.9 dB, +5.8 dB, +11.8 dB, +14.8 dB, +17.5 dB,
+19.5 dB
• DLE: ±0.5 LSB, ILE: ±1.25 LSB
• SFDR: 94 dB @ ƒIN = 900 kHz, –8.1 dBFS
• Internal sample-and-hold and voltage reference
• Power dissipation: 465 mW at 5 MSPS
• +5 V analog supply and +3.3 to +5.25 V digital output
supply
• 44-lead LQFP plastic package
• Data acquisition systems
• IR imaging
• Scanners and digital copiers
• High-end CCD cameras
• Medical imaging
• Wireless communications
• Lab and test equipment
• Automatic test equipment
DESCRIPTION
The SPT8100 is a high-performance, 16-bit analog-to-
digital converter that operates at a sample rate of up to
5 MSPS. Excellent dynamic performance and high linear-
ity is achieved by a digitally calibrated pipelined architec-
ture fabricated in CMOS process technology.
A low-noise programmable gain amplifier (PGA) is also in-
corporated on chip. The PGA is digitally programmable in
seven selected settings over a 0 to +19.5 dB range. The
SPT8100 also features an on-chip internal sample-and-
hold and internal reference for minimal external circuitry.
It operates from a single +5 V supply. Total power dissipa-
tion, including internal reference, is 465 mW. A separate
digital output supply pin is provided for +3.3 V or 5 V logic
output levels. The SPT8100 is available in a 44-lead LQFP
package over the industrial temperature range of –40 °C to
+85 °C.
BLOCK DIAGRAM
AVDD
+5V
DVDD
+5V
OVDD
+3/5 V
VIN+
VIN–
VCM
GS2 – GS0
(Gain Set)
Low-Noise
PGA
OE (Output Enable)
OVR (Over-Range)
16-bit, 5 MSPS ADC
16-bits
D15 – D0
(Data Outputs)
VREF
RS (Reset)
RDY (Ready)
AGND DGND OGND BIASC
(Ext Bias
Capacitor)
BIASR
(Ext Bias
Resistor)
VRT VRB
CLK
1 page  
initialization phase until RDY is deasserted. Note that,
although typically the device is initialized when power is
first applied, the initialization is only started when the RS is
asserted; there is no “power-on-reset” circuitry on chip. RS
may be held low for an indefinite period of time. While RS is
low, RDY will remain high. After RS is returned to high, RDY
will go low for the duration of the calibration.
PROGRAMMABLE GAIN AMPLIFIER
The programmable gain amplifier (PGA) precedes the
ADC inputs. The differential inputs, which are resistive, are
at pins VIN+ and VIN–.The maximum input range is 5 V
peak-to-peak differential (2.5 V single-ended). To achieve
maximum overall system noise performance, the source
driving these inputs needs to be as low-noise and as low-
jitter as possible, while maintaining the required distortion
performance. In addition, the driving source must be low
impedance to maintain the accuracy of the PGA gain.
TYPICAL INTERFACE CIRCUIT
ANALOG INPUT DRIVER
The differential analog inputs (VIN+, VIN–) have a resistive
input impedance of 1 kΩ minimum. For best performance,
the input source should be a differential input, as shown in
figure 2, typical interface circuit. The SPT8100 provides its
own common-mode voltage on the pin marked VCM. Out-
put drive capability of VCM is a maximum of 47 µA (50 kΩ to
ground).
The SPT8100 application note (AN8100) shows an ex-
ample of two modes of driving the SPT8100. One mode is
through a transformer and the other is through a single-to-
differential converter. In all cases, both inputs VIN+ and
VIN– must be kept within the input common-mode range
(1.15 V to 3.65 V).
BIASC CONNECTION
The internal 0 dB analog signal level and ADC full-scale
output level is 5 V peak-to-peak differential (2.5 V single-
ended). The PGA may be used to provide gain for an input
less than 5 V peak-to-peak differential.
An external capacitor, CEXT on the BIASC pin, is used only
for noise filtering of an internal voltage associated with the
references. Its value is not critical: 1 µF in parallel with
0.01 µF is recommended.
The gain of the PGA can be programmed using a three-bit
control, available at pins GS0 to GS2. See table I. Note that
the input resistance is a function of the gain setting.
Table I – PGA Gain Control
GS2 GS1 GS0
00
00
01
01
10
10
11
11
0
1
0
1
0
1
0
1
PGA Input
V/V
Gain Resistance Gain
(dB)
(kΩ)
3 dB
BW LSBRMS
0 5.57 1 12 1.4
2.9
4.65
1.40 10 1.5
5.8
3.97
1.95 8
1.6
11.8 2.23
3.9 7 2.0
14.8 1.66
5.5 6 2.3
17.5 1.25
7.5 5.5 2.6
19.5 1.00
9.5 5 2.8
X Forbidden
BIASR CONNECTION
As shown in the typical interface circuit, REXT is needed to
connect between BIASR to ground. This resistor ranges
from 800 Ω to 2.5 kΩ. The proper selection of REXT is a
function of the sample rate and input frequency. Nominally,
at 5 MSPS, REXT=1.43 kΩ is recommended. If linearity for
large signal levels at an analog bandwidth of 2 MHz is criti-
cal, the value should be decreased to REXT=1.24 kΩ; and
for even higher-frequency analog inputs, REXT=1.0 kΩ can
be used. At lower sample rates (for example 2 MSPS),
and lower analog input frequencies, the value may be in-
creased to REXT=2 kΩ. (Refer to the typical interface circuit
table in figure 2b.)
POWER SUPPLIES AND GROUNDING
The SPT8100 requires three power supplies: analog AVDD,
digital DVDD and output supply OVDD. This device works
best if all three supplies are coming from the analog supply
side of the system as shown in the typical interface circuit
(figure 2a).
Note, in figure 2a, that the supplies to the logic interface
circuit and the OVDD are separate from each other. In a
case where the +A3.3/5 V supply is not available, try to
implement the design as close as possible to that shown
in figure 2b. Place the ferrite bead (FB1) as close to the
device as possible. To avoid latch-up, the delta between
all three grounds must stay with 100 mV; this includes
transients. (Refer to the absolute maximum ratings
specifications.)
SPT8100
5 1/9/02
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