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PDF MC10319P Data sheet ( Hoja de datos )
| Número de pieza | MC10319P | |
| Descripción | High Speed8-Bit Analog-to-Digital Converter | |
| Fabricantes | Motorola Semiconductors | |
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Hay una vista previa y un enlace de descarga de MC10319P (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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High Speed 8-Bit
Analog-to-Digital Converter
MC10319
The MC10319 is an 8–bit high speed parallel flash A/D converter. The
device employs an internal Grey Code structure to eliminate large output
errors on fast slewing input signals. It is fully TTL compatible, requiring a
+ 5.0 V supply and a wide tolerance negative supply of – 3.0 to – 6.0 V.
Three–state TTL outputs allow direct drive of a data bus or common I/O
memory.
The MC10319 contains 256 parallel comparators across a precision input
reference network. The comparator outputs are fed to latches and then to an
encoder network, to produce an 8–bit data byte plus an overrange bit. The
data is latched and converted to 3–state LS–TTL outputs. The overrange bit
is always active to allow for either sensing of the overrange condition or ease
of interconnecting a pair of devices to produce a 9–bit A/D converter.
Applications include video display and radar processing, high speed
instrumentation and TV broadcast encoding.
• Internal Grey Code for Speed and Accuracy, Binary Outputs
• 8–Bit Resolution/9–Bit Typical Accuracy
• Easily Interconnected for 9–Bit Conversion
• 3–State LS–TTL Outputs with True/Complement Enable Inputs
• 25 MHz Sampling Rate
• Wide Input Range: 1.0 to 2.0 Vpp, between ± 2.0 V
• Low Input Capacitance: 50 pF
• Low Power Dissipation: 618 mW
• No Sample/Hold Required for Video Bandwidth Signals
• Single Clock Cycle Conversion
HIGH SPEED
8–BIT ANALOG–TO–DIGITAL
FLASH CONVERTER
SEMICONDUCTOR
TECHNICAL DATA
P SUFFIX
PLASTIC PACKAGE
CASE 709
DW SUFFIX
PLASTIC PACKAGE
CASE 751F
(SO–28L)
PIN CONNECTIONS
(P only)
Analog
Input
Vin
(14)
VRT
(24)
VRM
(1)
VRB
(23)
VCC(A)
(15)
Representative Block Diagram
Logic
GND
VEE
VCC(D)
(2, 12,
(13)
(11, 17)
16, 22)
Bias
MC10319
Bias
256
Comparators
Differential
Latch
Array
Grey Code
Translator
Output
Latches
and
ECL–TTL
Converters
Over–
Range
(3)
D7 (4)
D6 (5)
D5 (6)
D4 (7)
D3 (8)
D2 (9)
D1 (10)
D0 (21)
Clock
(18)
(19)
Enable
(20)
Enable
MOTOROLA ANALOG IC DEVICE DATA
VRM 1
GND 2
OVER–
RANGE
3
D7 4
D6 5
D5 6
D4 7
D3 8
D2 9
D1 10
VCC(D) 11
GND 12
24 VRT
23 VRB
22 GND
21 D0
20 EN
19 EN
18 CLOCK
17 VCC(D)
16 GND
15 VCC(A)
14 VIN
13 VEE
ORDERING INFORMATION
Device
Operating
Temperature Range Package
MC10319DW
MC10319P
TA = 0° to +70°C
SO–28L
Plastic
© Motorola, Inc. 1996
Rev 0
1
1 page  
Clock
tCKH
1.5 V
MC10319
Figure 1. System Timing Diagram
tCKL
1.5 V 1.5 V 1.5 V
3.0 V
Vin
D7–D0, OR
tAD
Sample 1
tCKDV
tH
Old Data
Sample 1
tAD
Sample 2
Sample 2
tCKDV and tH measured at output levels of 0.8 and 2.4 V.
EN 0.9 V
EN
High Data
Output
tEHZ
Low Data
Output
tELZ
3.0 V
0.9 V
tEDV
2.4 V
0.5 V
0.8 V
tEDV
0.4 V
3–State
3.0 V
tEDV
0.9 V
tEDV
0.8 V
Outputs
Active
0.5 V
0.9 V
tEDV
2.4 V
tEDV
0.4 V
Figure 2. Data Output Test Circuit
VCC
D0 – D7
C1
1.0 kΩ
3.0 kΩ
Diodes = 1N914 or equivalent, C1 ≈ 15 pF
Figure 3. Output 3–State Leakage Current
200
100
50
0
– 50
– 100
– 200
– 1.0
0
Pin 19 = 0 V
t t0°C TA 70°C
1.0 2.0 3.0 4.0 5.0
APPLIED VOLTAGE (VOLTS)
6.0
7.0
MOTOROLA ANALOG IC DEVICE DATA
5
5 Page 
VIDEO APPLICATIONS
MC10319
The MC10319 is suitable for digitizing video signals
directly without signal conditioning, although the standard
1.0 Vpp video signal can be amplified to a 2.0 Vpp signal for
slightly better accuracy. Figure 24 shows the input (top
trace) and reconstructed output of a standard NTSC test
signal, sampled at 25 MSPS, consisting of a sync pulse,
3.58 MHz color burst, a 3.58 MHz signal in a Sin2x
envelope, a pulse, a white level signal, and a black level
signal. Figure 25 shows a Sin2x pulse that has been
digitized and reconstructed at 25 MSPS. The width of the
pulse is ≈450 ns at the base. Figure 26 shows an application
circuit for digitizing video.
9–Bit A/D Converter
Figure 27 shows how two MC10319s can be connected to
form a 9–bit converter. In this configuration, the outputs
(D7 to D0) of the two 8–bit converters are paralleled. The
outputs of one device are active, while the outputs of the
other are in the 3–state mode. The selection is made by the
Overrange output of the lower MC10319, which controls
Enable inputs on the two devices. Additionally, this output
provides the 9th bit.
The reference ladders are connected in series, providing
the 512 steps required for 9 bits. The input voltage range is
determined by VRT of the upper MC10319, and VRB of the
lower device. A minimum of 1.0 volt is required across each
converter. The 500 Ω pot (20 turn cermet) allows for
adjustment of the midpoint since the reference resistors of
the two MC10319s may not be identical in value. Without the
adjustment, a non–equal voltage division would occur,
resulting in a nonlinear conversion. If the references are to be
symmetrical about ground (e.g., ± 1.0 V), the adjustment can
be eliminated, and the midpoint connected to ground. The
use of latches on the outputs is optional, depending on
the application.
50 MHz, 8–Bit A/D Converter
Figure 28 shows how two MC10319s can be connected
together in a flip–flop arrangement in order to have an
effective conversion speed of 50 MHz. The 74F74 D–type
flip–flop provides a 25 MHz clock to each converter, and at
the same time, controls the Enables so as to alternately
enable and disable the outputs. The Overranges do not have
3–state capability, and so cannot be paralleled. Instead they
are OR’d together. The use of latches is optional, and
depends on the application. Data should be latched, or
written to RAM (in a DMA operation), on the high–to–low
transition of the 50 MHz clock.
Negative Voltage Regulator
In the cases where a negative power supply is not
available (neither the – 3.0 to – 6.0 V, nor a higher negative
voltage from which to derive it), the circuit of Figure 29 can be
used to generate – 5.0 V from the + 5.0 V supply. The PC
board space required is small (≈ 2.0 in2), and it can be
located physically close to the MC10319. The MC34063A is
a switching regulator, and in Figure 29 is configured in an
inverting mode of operation. The regulator operating
specifications are also given.
Figure 16. Differential Phase and Gain Test
Video
Signal
(See Below)
Clock
MC10319
DUT
8
74F374
Latch
8
HDS–1250
12–Bit D/A
D3
D0
1.024 Vpp
to
Analyzer
285.7 mV
0
120 VRT
100
571.4 mV
(40 IRE)
80
60
40
2.000 V
1.429 V
(100 IRE)
20
– 20 IRE
Video Input Signal
1. Input waveform: 571.4 mVpp, sine wave @ 3.579545 MHz, dc levels as shown above.
2. MC10319 clock at 14.31818 MHz (4x) asynchronous to input.
3. Differential gain: peak–to–peak output @ each IRE level compared to that at 0 IRE.
4. Differential phase: Phase @ each IRE level compared to that @ 0 IRE.
VRB
MOTOROLA ANALOG IC DEVICE DATA
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MC10319P.PDF ] | |
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