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PDF COP688FH Data sheet ( Hoja de datos )
| Número de pieza | COP688FH | |
| Descripción | 8-Bit CMOS ROM Based Microcontrollers with 12k Memory/ Comparators/ USART and Hardware Multiply/Divide | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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September 1999
COP87L88GD/RD Family
8-Bit CMOS OTP Microcontrollers with 16k or 32k
Memory and 8-Channel A/D with Prescaler
General Description
The COP87L88GD/RD OTP (One Time Programmable)
Family microcontrollers are highly integratet COP8™ Fea-
ture core devices with 16k or 32k memory and advanced
features including an A/D Converter. These multi-chip CMOS
devices are suited for applications requiring a full featured
controller with an 8-bit A/D converter, and as pre-production
devices for a masked ROM design. Pin and software com-
patible 16k ROM versions are available (COP888GD), as
well as a range of COP8 software and hardware develop-
ment tools.
Family features include an 8-bit memory mapped architec-
ture, 10 MHz CKI (-XE = crystal oscillator) with 1µs instruc-
tion cycle, three multi-function 16-bit timer/counters,
MICROWIRE/PLUS™ serial I/O, one 8-bit/8-channel A/D
converter with prescaler and both differential and single
ended modes, two power saving HALT/IDLE modes, MIWU,
idle timer, high current outputs, software selectable I/O op-
tions, WATCHDOG™ timer and Clock Monitor, 2.7V to 5.5V
operation, program code security, and 44 pin package.
Devices included in this datasheet are:
Device
COP87L88GD
COP87L88RD
Memory (bytes)
16k EPROM
32k EPROM
RAM (bytes)
256
256
I/O Pins
40
40
Packages
44 PLCC
44 PLCC
Temperature
-40 to +85˚C
-40 to +85˚C
Key Features
n 8-channel A/D converter with prescaler and both
differential and single ended modes
n Idle Timer with 5 selectable Wake-Up periods
n Three 16-bit timers, each with two 16-bit registers
supporting:
— Processor Independent PWM mode
— External Event counter mode
— Input Capture mode
n 16 or 32 kbytes on-board OTP EPROM with security
feature
n 256 bytes on-board RAM
Additional Peripheral Features
n Multi-Input Wakeup (MIWU) with optional interrupts (8)
n WATCHDOG and clock monitor logic
n MICROWIRE/PLUS serial I/O
I/O Features
n Memory mapped I/O
n Software selectable I/O options (TRI-STATE® Output,
Push-Pull Output, Weak Pull Up Input, High Impedance
Input)
n Schmitt trigger inputs on ports G and L
n Package:
— 44 PLCC with 40 I/O pins
CPU/Instruction Set Features
n 1 µs instruction cycle time
n Twelve multi-source vectored interrupts servicing
— External Interrupt
— Idle Timer T0
— Three Timers (each with 2 Interrupts)
— MICROWIRE/PLUS
— Multi-Input Wake Up
— Software Trap
— Default VIS (default interrupt)
n Versatile and easy to use instruction set
n 8-bit Stack Pointer (SP) – stack in RAM
n Two 8-bit Register Indirect Data Memory Pointers (B
and X)
Fully Static CMOS
n Two power saving modes: HALT and IDLE
n Single supply operation: 2.7V to 5.5V
n Temperature range: −40˚C to +85˚C
Development Support
n Emulation device for COP888GD
n Real time emulation and full program debug offered by
MetaLink Development System
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
MICROWIRE/PLUS™, COP8™, MICROWIRE™ and WATCHDOG™ are trademarks of National Semiconductor Corporation.
iceMASTER® is a registered trademark of MetaLink Corporation.
© 1999 National Semiconductor Corporation DS012526
www.national.com
1 page  
AC Electrical Characteristics
−40˚C ≤ TA ≤ +85˚C unless otherwise specified
Parameter
Conditions
Min Typ Max Units
Instruction Cycle Time (tc)
Crystal, Resonator,
R/C Oscillator
CKI Clock Duty Cycle (Note 9)
Rise Time (Note 9)
Fall Time (Note 9)
Inputs
4.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
fr = Max
fr = 10 MHz Ext Clock
fr = 10 MHz Ext Clock
1.0
3.0
40
DC µs
DC µs
60 %
5 ns
5 ns
tSETUP
tHOLD
Output Propagation Delay (Note 8)
tPD1, tPD0
SO, SK
All Others
MICROWIRE™ Setup Time (tUWS) (Note 9)
MICROWIRE Hold Time (tUWH) (Note 9)
MICROWIRE Output Propagation Delay (tUPD)
Input Pulse Width (Note 9)
4.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
RL = 2.2k, CL = 100 pF
4.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
200
60
20
56
ns
ns
0.7 µs
1.0 µs
ns
ns
220 ns
Interrupt Input High Time
Interrupt Input Low Time
Timer 1, 2, 3 Input High Time
Timer 1, 2, 3 Input Low Time
Reset Pulse Width
1.0 tc
1.0 tc
1.0 tc
1.0 tc
1.0 µs
Note 2: tc = Instruction Cycle Time
Note 3: Maximum rate of voltage change must be < 0.5 V/ms.
Note 4: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to VCC
and outputs driven low but not connected to a load.
Note 5: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations by bringing CKI high. Measurement of IDD HALT is done with device
neither sourcing nor sinking current; with L, C, G0, and G2–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load;
all inputs tied to VCC; clock monitor and comparator disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up
CKI during HALT in crystal clock mode.
Note 6: The user must guarantee that D2 pin does not source more than 10 mA during RESET. If D2 sources more than 10 mA during reset, the device will go into
programming mode.
Note 7: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when
biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typical). These two
pins will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes
ESD transients.
Note 8: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 9: Parameter characterized but not tested.
5 www.national.com
5 Page 
Oscillator Circuits (Continued)
DS012526-8
DS012526-9
FIGURE 7. Crystal and R/C Oscillator Diagrams
TABLE 1. Crystal Oscillator Configuration, TA = 25˚C
R1 R2 C1
C2 CKI Freq Conditions
(kΩ)
0
0
0
(MΩ)
1
1
1
(pF) (pF)
30 30–36
30 30–36
200 100–150
(MHz)
10
4
0.455
VCC = 5V
VCC = 5V
VCC = 5V
TABLE 2. RC Oscillator Configuration, TA = 25˚C
R C CKI Freq Instr. Cycle Conditions
(kΩ)
3.3
5.6
6.8
(pF)
82
100
100
(MHz)
2.2 to 2.7
1.1 to 1.3
0.9 to 1.1
(µs)
3.7 to 4.6
7.4 to 9.0
8.8 to 10.8
VCC = 5V
VCC = 5V
VCC = 5V
Note 14: 3k ≤ R ≤ 200k
50 pF ≤ C ≤ 200 pF
CONTROL REGISTERS
CNTRL Register (Address X'00EE)
T1C3 T1C2 T1C1 T1C0 MSEL IEDG SL1 SL0
Bit 7
Bit 0
The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:
T1C3
Timer T1 mode control bit
T1C2
Timer T1 mode control bit
T1C1
Timer T1 mode control bit
T1C0
Timer T1 Start/Stop control in timer
modes 1 and 2, T1 Underflow Interrupt
Pending Flag in timer mode 3
MSEL
Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively
IEDG
External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)
SL1 & SL0 Select the MICROWIRE/PLUS clock divide
by (00 = 2, 01 = 4, 1x = 8)
PSW Register (Address X'00EF)
HC C T1PNDA T1ENA EXPND BUSY EXEN GIE
Bit 7
Bit 0
The PSW register contains the following select bits:
HC Half Carry Flag
C Carry Flag
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload
RA in mode 1, T1 Underflow in Mode 2, T1A
capture edge in mode 3)
T1ENA Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge
EXPND External interrupt pending
BUSY MICROWIRE/PLUS busy shifting flag
EXEN Enable external interrupt
GIE Global interrupt enable (enables interrupts)
The Half-Carry flag is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and R/C (Reset
Carry) instructions will respectively set or clear both the carry
flags. In addition to the SC and R/C instructions, ADC,
SUBC, RRC and RLC instructions affect the Carry and Half
Carry flags.
ICNTRL Register (Address X'00E8)
Reserved LPEN T0PND T0EN µWPND µWEN T1PNDB T1ENB
Bit 7
Bit 0
The ICNTRL register contains the following bits:
Reserved This bit is reserved and should to zero
LPEN
L Port Interrupt Enable (Multi-Input Wakeup/
Interrupt)
T0PND Timer T0 Interrupt pending
T0EN Timer T0 Interrupt Enable (Bit 12 toggle)
µWPND MICROWIRE/PLUS interrupt pending
µWEN Enable MICROWIRE/PLUS interrupt
T1PNDB Timer T1 Interrupt Pending Flag for T1B cap-
ture edge
T1ENB Timer T1 Interrupt Enable for T1B Input cap-
ture edge
T2CNTRL Register (Address X'00C6)
T2C3 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB
Bit 7
Bit 0
The T2CNTRL control register contains the following bits:
T2C3
Timer T2 mode control bit
T2C2
Timer T2 mode control bit
T2C1
Timer T2 mode control bit
T2C0
Timer T2 Start/Stop control in timer
modes 1 and 2, T2 Underflow Interrupt Pend-
ing Flag in timer mode 3
T2PNDA Timer T2 Interrupt Pending Flag (Autoreload
RA in mode 1, T2 Underflow in mode 2, T2A
capture edge in mode 3)
T2ENA Timer T2 Interrupt Enable for Timer Underflow
or T2A Input capture edge
T2PNDB Timer T2 Interrupt Pending Flag for T2B cap-
ture edge
11 www.national.com
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| PDF Descargar | [ Datasheet COP688FH.PDF ] | |
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