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PDF LPC812M101FD20 Data sheet ( Hoja de datos )
| Número de pieza | LPC812M101FD20 | |
| Descripción | 32-bit ARM Cortex-M0+ microcontroller | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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LPC81xM
32-bit ARM Cortex-M0+ microcontroller; up to 16 kB flash and
4 kB SRAM
Rev. 1 — 12 November 2012
Objective data sheet
1. General description
The LPC81xM are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at
CPU frequencies of up to 30 MHz. The LPC81xM support up to 16 kB of flash memory
and 4 kB of SRAM.
The peripheral complement of the LPC81xM includes a CRC engine, one I2C-bus
interface, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self wake-up
timer, and state-configurable timer, one comparator, function-configurable I/O ports
through a switch matrix, an input pattern match engine, and up to 18 general-purpose I/O
pins.
2. Features and benefits
System:
ARM Cortex-M0+ processor, running at frequencies of up to 30 MHz with
single-cycle multiplier and fast single-cycle I/O port.
ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).
System tick timer.
Serial Wire Debug (SWD) and JTAGwww.DataSheet.net/ boundary scan modes supported.
Micro Trace Buffer (MTB) supported.
Memory:
Up to 16 kB on-chip flash programming memory with 64 Byte page write and erase.
4 kB SRAM.
ROM API support:
Boot loader.
USART drivers.
I2C drivers.
Power profiles.
Flash In-Application Programming (IAP) and In-System Programming (ISP).
Digital peripherals:
High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to 18
General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors.
GPIO interrupt generation capability with boolean pattern-matching feature on eight
GPIO inputs.
Switch matrix for flexible configuration of each I/O pin function.
State Configurable Timer (SCT) with input and output functions (including capture
and match) assigned to pins through the switch matrix.
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
NXP Semiconductors
6. Pinning information
6.1 Pinning
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
5(6(73,2B
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DDD
Fig 2. Pin configuration DIP8 package (LPC810M021FN8)
3,2B
3,2B
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6:',23,2B706
3,2B
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966
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3,2B ;7$/287
3,2B$&03B,&/.,17',
DDD
www.DataSheet.net/
Fig 3. Pin configuration TSSOP16 package
3,2B
3,2B
3,2B
5(6(73,2B
3,2B:$.(837567
6:&/.3,2B7&.
6:',23,2B706
3,2B
3,2B
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62
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3,2B
DDD
Fig 4. Pin configuration SO20 package (LPC812M101FD20)
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 November 2012
© NXP B.V. 2012. All rights reserved.
5 of 67
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
NXP Semiconductors
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
7. Functional description
7.1 ARM Cortex-M0+ core
The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz using a
two-stage pipeline. Integrated in the core are the NVIC and Serial Wire Debug with four
breakpoints and two watchpoints. The ARM Cortex-M0+ core supports a single-cycle I/O
enabled port for fast GPIO access.
The core includes a single-cycle multiplier and a system tick timer.
7.2 On-chip flash program memory
The LPC81xM contain up to 16 kB of on-chip flash program memory. The flash memory
supports a 64 Byte page size with page write and erase.
7.3 On-chip SRAM
The LPC81xM contain a total of 1 kB, 2 kB, or 4 kB on-chip static RAM data memory.
7.4 On-chip ROM
The 8 kB on-chip ROM contains the boot loader and the following Application
Programming Interfaces (API):
• In-System Programming (ISP) and In-Application Programming (IAP) support for flash
programming
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• Power profiles for configuring power consumption and PLL settings
• USART driver API routines
• I2C-bus driver API routines
7.5 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0+. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
7.5.1 Features
• Controls system exceptions and peripheral interrupts.
• In the LPC81xM, the NVIC supports 32 vectored interrupts including up to 8 external
interrupt inputs selectable from all GPIO pins.
• Four programmable interrupt priority levels with hardware priority level masking.
• Software interrupt generation using the ARM exceptions SVCall and PendSV.
• Relocatable interrupt vector table.
7.5.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 November 2012
© NXP B.V. 2012. All rights reserved.
11 of 67
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