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PDF LPC3152 Data sheet ( Hoja de datos )
| Número de pieza | LPC3152 | |
| Descripción | (LPC3152 / LPC3154) ARM926EJ microcontrollers | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LPC3152 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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LPC3152/3154
ARM926EJ microcontrollers with USB High-speed OTG,
SD/MMC, NAND flash controller, and audio codec
Rev. 1 — 31 May 2012
Product data sheet
1. General description
The NXP LPC3152/3154 combine an 180 MHz ARM926EJ-S CPU core, High-speed USB
2.0 OTG, 192 kB SRAM, NAND flash controller, flexible external bus interface, an
integrated audio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and
parallel interfaces in a single chip targeted at consumer, industrial, medical, and
communication markets. To optimize system power consumption, the LPC3152/3154
have multiple power domains and a very flexible Clock Generation Unit (CGU) that
provides dynamic clock gating and scaling.
The LPC3152/3154 are implemented as a multi-chip module with two side-by-side dies,
one for digital functions and one for analog functions, which include Power Supply Unit
(PSU), audio codec, RTC, and Li-ion battery charger.
2. Features and benefits
2.1 Key features
CPU platform
www.DataSheet.net/
180 MHz, 32-bit ARM926EJ-S
16 kB D-cache and 16 kB I-cache
Memory Management Unit (MMU)
Internal memory
192 kB embedded SRAM
External memory interface
NAND flash controller with 8-bit ECC and AES decryption engine (LPC3154 only)
8/16-bit Multi-Port Memory Controller (MPMC): SDRAM and SRAM
Security
AES decryption engine (LPC3154 only)
Secure one-time programmable memory for AES key storage and customer use
128 bit unique ID per device for DRM schemes
Communication and connectivity
High-speed USB 2.0 (OTG, Host, Device) with on-chip PHY
Two I2S-bus interfaces
Integrated master/slave SPI
Two master/slave I2C-bus interfaces
Fast UART
Memory Card Interface (MCI): MMC/SD/SDIO/CE-ATA
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
NXP Semiconductors
LPC3152/3154
ARM926EJ microcontrollers
5. Pinning information
5.1 Pinning
ball A1
index area 2 4 6 8 10 12 14 16
1 3 5 7 9 11 13 15 17
A
B
C
D
E
F
G
H
J LPC3152/
K LPC3154
L
M
N
P
R
T
U
002aae464
Transparent top view
Fig 2. LPC3152/3154 pinning TFBGA208 package
Table 3. Pin allocation table
www.DataSheet.net/
Pin names with prefix m are multiplexed pins. See Table 11 for pin function selection of multiplexed pins.
Pin Symbol
Pin Symbol
Pin Symbol
Pin Symbol
Row A
1 n.c.
2 EBI_A_1_CLE
3 EBI_D_9
4 VDDE_IOC
5 VSSE_IOC
6 VDDI
7 VSSI
8 SPI_MISO
9 I2C_SCL0
10 FFAST_IN
11 n.c.
12 n.c.
13 ADC10B_GNDA
14 VSSE_IOC
15 VDDE_IOC
16 HP_VDDA33
17 n.c.
-
-
-
Row B
1 n.c.
2 n.c.
3 n.c.
4 n.c.
5 mNAND_RYBN0
6 mGPIO9
7 mGPIO6
8 SPI_MOSI
9 n.c.
10 FFAST_OUT
11 VDDA12
12 ADC10B_GPA0
13 ADC10B_VDDA33
14 n.c.
15 HP_FCR
16 HP_GNDA
17 HP_OUTL
-
-
-
Row C
1 n.c.
2 EBI_D_10
3 n.c.
4 EBI_A_0_ALE
5 mNAND_RYBN1
6 mGPIO10
7 mGPIO7
8 SPI_SCK
9 VPP
10 I2C_SDA0
11 VSSA12
12 ADC10B_GPA2
13 ADC10B_GPA1
14 DAC_VDDA33
15 HP_OUTR
16 HP_FCL
17 PSU_PLAY
-
-
-
Row D
1 VDDE_IOA
2 EBI_D_11
3 EBI_D_8
4 mNAND_RYBN3
LPC3152_54
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 31 May 2012
© NXP B.V. 2012. All rights reserved.
5 of 94
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
NXP Semiconductors
LPC3152/3154
ARM926EJ microcontrollers
Table 4. Pin description …continued
Pin names with prefix m are multiplexed pins. See Table 11 for pin function selection of multiplexed pins.
TFBGA pin name
TFB
GA
ball
Digital
I/O
level
[1]
Application
function
Pin
state
after
reset[2]
Cell type
[3]
Description
I2SRX_BCK0[4]
T9 SUP3 DIO / GPIO I
DIO1
I2S input bitclock
I2SRX_WS0[4]
R9 SUP3 DIO / GPIO I
DIO1
I2S input word select
I2S/Digital audio output
mI2STX_DATA0[4]
T13 SUP3 DO / GPIO O
DIO1
I2S output serial data out
mI2STX_BCK0[4]
T12 SUP3 DO / GPIO O
DIO1
I2S output bitclock
mI2STX_WS0[4]
R12 SUP3 DO / GPIO O
DIO1
I2S output word select
mI2STX_CLK0[4]
T11 SUP3 DO / GPIO O
DIO1
I2S output serial clock
General Purpose IO (IOCONFIG module)
GPIO0[8]
R13 SUP3 GPIO
I:PD DIO1
General Purpose IO pin 0 (mode pin 0)
GPIO1[8]
T14 SUP3 GPIO
I:PD DIO1
General Purpose IO pin 1 (mode pin 1)
GPIO2[8]
P12 SUP3 GPIO
I
DIO1
General Purpose IO pin 2 (mode
pin 2/blinking LED)
GPIO3
D12 SUP3 GPIO
I
DIO1
General Purpose IO pin 3 (connect to
PSU_STOP)[5]
GPIO4
D11 SUP3 GPI
I
DIO1
General Purpose Input pin 4
mGPIO5[4]
D7 SUP3 GPIO
I
DIO4
General Purpose IO pin 5
mGPIO6[4]
mGPIO7[4]
B7 SUP3 GPIO
C7 SUP3 GPIO
I
DIO4
General Purpose IO pin 6
www.DataSheet.net/
I
DIO4
General Purpose IO pin 7
mGPIO8[4]
D6 SUP3 GPIO
I
DIO4
General Purpose IO pin 8
mGPIO9[4]
B6 SUP3 GPIO
I
DIO4
General Purpose IO pin 9
mGPIO10[4]
C6 SUP3 GPIO
I
DIO4
General Purpose IO pin 10
External Bus Interface (NAND flash controller)
EBI_A_0_ALE[4]
C4 SUP4 DO
O
DIO4
EBI Address Latch Enable (ALE)
EBI_A_1_CLE[4]
A2 SUP4 DO
O
DIO4
EBI Command Latch Enable (CLE)
EBI_D_0[4]
J3 SUP4 DIO
I
DIO4
EBI Data I/O 0
EBI_D_1[4]
H3 SUP4 DIO
I
DIO4
EBI Data I/O 1
EBI_D_2[4]
H4 SUP4 DIO
I
DIO4
EBI Data I/O 2
EBI_D_3[4]
G4 SUP4 DIO
I
DIO4
EBI Data I/O 3
EBI_D_4[4]
F4 SUP4 DIO
I
DIO4
EBI Data I/O 4
EBI_D_5[4]
F3 SUP4 DIO
I
DIO4
EBI Data I/O 5
EBI_D_6[4]
E4 SUP4 DIO
I
DIO4
EBI Data I/O 6
EBI_D_7[4]
E3 SUP4 DIO
I
DIO4
EBI Data I/O 7
EBI_D_8[4]
D3 SUP4 DIO
I
DIO4
EBI Data I/O 8
EBI_D_9[4]
A3 SUP4 DIO
I
DIO4
EBI Data I/O 9
EBI_D_10[4]
C2 SUP4 DIO
I
DIO4
EBI Data I/O 10
EBI_D_11[4]
D2 SUP4 DIO
I
DIO4
EBI Data I/O 11
EBI_D_12[4]
E2 SUP4 DIO
I
DIO4
EBI Data I/O 12
EBI_D_13[4]
F2 SUP4 DIO
I
DIO4
EBI Data I/O 13
LPC3152_54
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 31 May 2012
© NXP B.V. 2012. All rights reserved.
11 of 94
Datasheet pdf - http://www.DataSheet4U.co.kr/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LPC3152.PDF ] | |
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