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PDF ISL6112 Data sheet ( Hoja de datos )
| Número de pieza | ISL6112 | |
| Descripción | Dual Slot PCI-Express Power Controller | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
Data Sheet
September 28, 2007
ISL6112
FN6456.0
Dual Slot PCI-Express Power Controller
The ISL6112 targets the PCI-Express add-in card hot plug
application. Together with two each of N-Channel and
P-Channel MOSFETs, four current sense resistors and
several external passive components the ISL6112 provides
a compliant hot plug power control solution to any
combination of two PCI-Express X1, X4, X8 or X16 slots.
The ISL6112 features the ability to program a maximum
current regulated level for each of the MAIN outputs for a
common programmable duration so that both fault isolation
protection and imperviousness to electrical transients (OC
and soft-start protection) are provided to each system
supply. For each 12VMAIN supply, the current regulated
(CR) level is set by a resistor value dependant on the size of
the PCI-Express connector (X1, X4/X8 or X16) to be
powered. This resistor is a sub ohm standard value current
sense resistor one each for each of the 3VMAIN and
12VMAIN supplies. The voltage across this resistor is
compared to a 50mV reference providing a nominal CR
protection level which would be set above the maximum
specified slot limits. The 3.3V supply can use a 15mΩ sense
resistor compared to a 50mV reference to provide a nominal
regulated current limit of 3.3A to all connector sizes. A
shutdown without a CR duration delay is invoked if RSENSE
voltage is >100mV. The VAUX is internally monitored and
controlled to provide nominal limiting to 1A of load current.
The ISL6112 is System Management Interface (SMI)
capable with an integrated SMBus link for communication,
control, monitoring and reporting of IC and slot conditions.
Information such as UV, OC, STATUS, power level etc. are
available. Additionally the IC has a minimum of I/O for
implementations where Hot-Plug Hardware Interface (HPI) is
implemented.
Features
• Supports Two Independent PCI Express Slots
• Highest Available Accuracy External RSENSE Current
Monitoring on Main Supplies
• Programmable Current Regulation Protection Function for
X1, X4, X8, X16 Connectors
• 12V, 3.3V, and 3.3VAUX Supplies Supported per PCI
Express Specification V1.0A
• Voltage Tolerant I/O SMBus Interface for Slot Power
Control and Status, compatible with SMBus 2.0 Systems
• Programmable Current Regulation Duration
• Programmable In-rush Current Limiting
• Dual Level Fault Detection for Quick Fault Response
without Nuisance Tripping
• Slot to Slot Electrical and Thermal Isolation
• Two General Purpose Input Pins Suitable for Interface to
Logic and Switches.
• TQFP or QFN Pb-Free Package Options
- TQFP is pin for pin equivalent to MIC2592B-2YTQ and
is compatible with the TPS2363 pinout
- The QFN package is 40% smaller and has lower die to
case thermal impedance than the TQFP
• Pb-Free (RoHS Compliant)
Applications
• PCI Express V1.0A hot-plug power control
• PCI-Express Servers
• Power Supply Distribution and Control
Ordering Information
PART NUMBER
(Note)
PART MARKING
TEMP RANGE (°C)
PACKAGE
(Pb-Free)
PKG. DWG. #
ISL6112IRZA
ISL6112 IRZ
-40 to +85
48 Ld 7x7 QFN
L48.7x7
ISL6112IRZA-T*
ISL6112 IRZ
-40 to +85
48 Ld 7x7 QFN Tape and Reel
L48.7x7
ISL6112INZA
ISL6112 INZ
-40 to +85
48 Ld 7x7 TQFP
Q48.7x7
ISL6112INZA-T*
ISL6112 INZ
-40 to +85
48 Ld 7x7 TQFP Tape and Reel
Q48.7x7
wwwI.SDLa6t1a1S2hEeVeAtL41UZ.com
Evaluation Platform
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6112
Pin Descriptions (Pin Numbers and Names are Related) (Continued)
PIN NUMBER
PIN NAME
PIN FUNCTION
1, 36
FAULTA, FAULTB
Fault Outputs: Open-drain, active-low. Asserted whenever the isolation protection trips due to a fault
condition (overcurrent, input undervoltage, over-temperature). Each pin requires an external pull-up
resistor to VSTBY. Bringing the slot’s ON pin low resets FAULT if FAULT was asserted in response to a
fault condition on one of the slot’s MAIN outputs (+12V or +3.3V). FAULT is reset by bringing the slot’s
AUXEN pin low if FAULT was asserted in response to a fault condition on the slot’s VAUX output. If a fault
condition occurred on both the MAIN and VAUX outputs of the same slot, then both ON and AUXEN must
be brought low to de-assert the FAULT output.
9, 28
FORCE_ONA
FORCE_ONB
Enable Inputs: Active-low, level-sensitive. Asserting a FORCE_ON input will turn on all three of the
respective slot’s outputs (+12V, +3.3V, and VAUX), while specifically defeating all protections on those
supplies. This explicitly includes all overcurrent and short circuit protections, and on-chip thermal
protection for the VAUX supplies. Additionally included are the UVLO protections for the +3.3V and
+12VMAIN supplies. The FORCE_ON pins do not disable UVLO protection for the VAUX supplies. These
input pins are intended for diagnostic purposes only. Asserting FORCE_ON will cause the respective slot’s
PWRGD and FAULT pins to enter their open-drain state. Note that the SMBus register set will continue to
reflect the actual state of each slot’s supplies. There is a pair of register bits, accessible via the SMBus,
which can be set to disable (unconditionally de-assert) either or both of the FORCE_ON pins -- See
CNTRL Register Bit D[2].
4, 38
GPI_A0, GPI_B0 General Purpose Inputs: The states of these two inputs are available by reading the Common Status
Register, Bits [4:5]. If not used, connect each pin to GND.
39, 40, 41
A2, A1, A0
SMBus Address Select Pins. Connect to ground or leave open in order to program device SMBus base
address. These inputs have internal pull-up resistors to VSTBY. Address programmed on rising VSTBY.
48
SDA
Bidirectional SMBus data line.
47
SCL
SMBus Clock Input.
37 INT Interrupt Output. Open-drain, active-low. output. Asserted whenever a power fault is detected if the
INTMSK bit (CS Register Bit D[3]) is a logical “0”. This output is cleared by performing an “echo reset” to
the appropriate fault bit(s) in the STAT and/or CS registers. This pin requires an external pull-up resistor
to VSTBY.
17, 33, 46
GND
IC Reference pins. Connect together and tie directly to the system’s analog GND plane directly at the
device.
7, 18, 19, 20, 30
NC Reserved: Make no external connections to these pins.
www.DataSheet4U.com
5
FN6456.0
September 28, 2007
5 Page 
VSTBY
INT
100k
100k
100k
SCL
SDA
INT#
A2
A1
A0
DISABLING SMI WHEN HPI CONTROL IS USED
VSTBY
100k 9
100k 28
45
42
44
43
FORON#_A
FORON#_B
AUXENA
AUXENB
ONA
ONB
ISL6112
deasserted or else the ISL6112 will assert its FAULT outputs.
If an undervoltage condition on either of the MAIN supply
inputs is detected, the INT will also assert if interrupts are
enabled.
VAAUUXX
AAUUXXEENN
IAAUUXX
DISABLING HPI WHEN SMI CONTROL IS USED
FIGURE 1. I/O CONFIGURATION FOR DISABLING HPI/SMI
CONTROL
ISL6112 Bias, Power-On Reset and Power Cycling
The ISL6112 utilizes VSTBY as the only supply source.
VSTBY is required for proper operation of the ISL6112’s
SMBus and registers and must be applied at all times. A
Power-On Reset (POR) cycle is initiated after VSTBY rises
above its UVLO threshold and remains satisfied for 250µs.
All internal registers are cleared after POR. If VSTBY is
recycled, the ISL6112 enters a new power-on-reset cycle.
VSTBY must be the first supply voltage applied followed by
the MAIN supply inputs of 12VIN and 3VIN. The SMBus is
ready for access at the end of the POR cycle (250µs after
VSTBY is valid). During tPOR, all outputs remain off.
Enabling the VAUX Outputs
Upon asserting an AUXEN input, the related internal power
switch turns on connecting the nominally 3.3V VSTBY
supply to its VAUX load. The turn-on is slew rate limited and
invokes the ICs current regulation feature so as to not droop
the supply due to in-rush current load. Figure 2 illustrates the
VAUX turn-on performance into a 10Ω, 100µF load.
Standby Mode
Standby mode is entered when one or more of the MAIN
supply inputs (12VIN and/or 3VIN) is absent, below its
respective UVLO threshold or OFF. The ISL6112 also has
3.3V auxiliary outputs (VAUXA and VAUXB), satisfying an
optional PCI Express requirement. These outputs are fed
wwwfr.DomatathSeheVeSt4TUB.Ycoimnput pins, they are independent of the
MAIN outputs and are controlled by the AUXEN input pins or
via their respective bits in the control registers. Should the
MAIN supply inputs fall below their respective UVLO
thresholds, VAUX will still function as long as VSTBY is
compliant. Prior to standby mode, ONA and ONB (or the
control registers' MAINA and MAINB bits) inputs must be
FIGURE 2. VAUX TURN-ON RLOAD = 10Ω, CLOAD = 100µF
Enabling the MAIN GATE outputs
When a slot's MAIN supplies are off, the 12VGATE pin is
held high with an internal pull-up to the 12VIN voltage.
Similarly, the 3VGATE pin is internally held low to GND.
When the MAIN supplies of the ISL6112 are enabled by
asserting ON, the related 3VGATE and 12VGATE pins are
each connected to a constant current supply. For the
3VGATE pin, this is nominally a 25µA current source and for
the 12VGATE pin, this is nominally a -25µA current sink. The
3VGATE will be charged up to the 12VIN voltage whereas
the 12GATE will be pulled down to GND for maximum
enhancement of the N-Channel and P-Channel FETs,
respectively.
Estimating In-Rush Current and VOUT Slew Rate at
Start-up
The expected in-rush current can be estimated by using
Equation 1:
IIN – RUSHNOMINALLY
=
⎛
25 μ A ⎜
⎝
CC-----LG---O--A---AT----DE--⎠⎟⎞
(EQ. 1)
with 25µA being the GATE pin charge current, CLOAD is the
load capacitance, and CGATE is the total GATE capacitance
including CISS of the external MOSFET and any external
capacitance connected from the GATE output pin to the
GATE reference, GND or source.
An estimate for the output slew rate of 3.3V outputs and 12V
outputs where there is little or no external 12VGATE output
capacitors, can be had from Equation 2:
dv/dt VOUT
NOMINALLY
=
-----I--L---I--M-------
CLOAD
(EQ. 2)
11 FN6456.0
September 28, 2007
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ISL6112.PDF ] | |
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