PDF LPC47N252 Data sheet ( Hoja de datos )

Número de pieza	LPC47N252
Descripción	Advanced Notebook I/O Controller with On-Board FLASH
Fabricantes	SMSC Corporation
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LPC47N252 PRELIMINARY _ Advanced Notebook I/O Controller with On-Board FLASH FEATURES § 3.3V Operation with 5V Tolerant Buffers § ACPI 1.0b , PC99/PC2001 Compliant § LPC Interface with Clock Run Support − Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems − 15 Direct IRQs − Four 8-Bit DMA Channels − ACPI SCI Interface − nSMI − Shadowed write only registers § Internal 64K Flash ROM − Programmed From Direct Parallel Interface, 8051, or LPC Host − 2k-Byte Lockable Boot Block − Can be Programed Without 8051 Intervention § Three Power Planes − Low Standby Current in Sleep Mode − Intelligent Auto Power Management for Super I/O § ACPI Embedded Controller Interface § Configuration Register Set Compatible with ISA Plug-and-Play Standard (Version 1.0a) § High-Performance Embedded 8051 Keyboard and System Controller − Provides System Power Management − System Watch Dog Timer (WDT) − 8042 Style Host Interface − Supports Interrupt and Polling Access − 256 Bytes Data RAM − On-Chip Memory-Mapped Control Registers − Access to RTC and CMOS Registers − Up to 16x8 Keyboard Scan Matrix − Two 16 Bit Timer/Counters − Integrated Full-Duplex Serial Port Interface − Eleven 8051 Interrupt Sources − Thirty-Two 8-Bit, Host/8051 Mailbox Registers − Thirty-six Maskable Hardware Wake-Up Events − Fast GATEA20 − Fast CPU_RESET − Multiple Clock Sources and Operating Frequencies − IDLE and SLEEP Modes − Fail-Safe Ring Oscillator § Advanced Infrared Communications Controller (IrCC 2.0) − IrDA V1.2 (4Mbps), HPSIR, ASKIR, Consumer IR Support − Two IR Ports − Relocatable Base I/O Address § Real-Time Clock − MC146818 and DS1287 Compatible − 256 Bytes of Battery Backed CMOS in Two 128-Byte Banks − 128 Bytes of CMOS RAM Lockable in 4x32 Byte Blocks − 12 and 24 Hour Time Format − Binary and BCD Format − <2µA Standby Current (typ) § Two 8584-Style ACCESS.Bus Controllers − 8051 Controlled Logic Allows ACCESS.Bus Master or Slave Operation − ACCESS.Bus Controllers are Fully Operational on Standby Power − 2 Sets of Dedicated Pins per ACCESS.BusController § Four independent Hardware Driven PS/2 Ports § 83 General Purpose I/O Pins − 36 Maskable Hardware Wake-Event Capable − 18 Programmable Open-Drain/Push-Pull Outputs − 16 Mapped into 8051 SFR Space − 24 LPC/8051-Addressable § Three Programmable Pulse-Width Modulator Outputs − Independent Clock Rates − 6 Bit Duty Cycle Granularity Note: Please see Addendum to LPC47N252 Data Sheet at http://www.smsc.com/main/datasheets/47n252add.pdf SMSC DS – LPC47N252 Rev. 09/06/2000 1 page 5.7.1 Read Data............................................................................................................................................. 61 5.7.2 Read Deleted Data ............................................................................................................................... 62 5.7.3 Read A Track........................................................................................................................................ 63 5.7.4 Write Data............................................................................................................................................. 64 5.7.5 Write Deleted Data ............................................................................................................................... 64 5.7.6 Verify..................................................................................................................................................... 64 5.7.7 Format A Track ..................................................................................................................................... 65 5.8 FDC CONTROL COMMANDS ..................................................................................................................... 67 5.8.1 Read ID................................................................................................................................................. 67 5.8.2 Recalibrate............................................................................................................................................ 67 5.8.3 Seek...................................................................................................................................................... 67 5.8.4 Sense Interrupt Status .......................................................................................................................... 68 5.8.5 Sense Drive Status ............................................................................................................................... 68 5.8.6 Specify .................................................................................................................................................. 68 5.8.7 Configure .............................................................................................................................................. 69 5.8.8 Version.................................................................................................................................................. 69 5.8.9 Relative Seek........................................................................................................................................ 70 5.8.10 Perpendicular Mode.............................................................................................................................. 70 5.8.11 Lock ...................................................................................................................................................... 71 5.8.12 Enhanced DUMPREG .......................................................................................................................... 72 5.9 COMPATIBILITY .......................................................................................................................................... 72 5.9.1 Parallel Port FDC.................................................................................................................................. 72 5.9.2 Hot Swappable FDD Capability ............................................................................................................ 72 5.10 FDC FORCE WRITE PROTECT .................................................................................................................. 73 6 ACPI EMBEDDED CONTROLLER...................................................................................................................... 75 6.1 ECI CONFIGURATION REGISTERS ..................................................................................................................... 75 6.2 ECI RUNTIME REGISTERS................................................................................................................................ 76 6.3 EC_STATUS REGISTER................................................................................................................................. 76 6.4 EC_COMMAND REGISTER............................................................................................................................ 77 6.5 EC_DATA REGISTER ..................................................................................................................................... 78 7 SERIAL PORT (UART) ........................................................................................................................................ 79 7.1 REGISTER DESCRIPTION.......................................................................................................................... 79 7.1.1 Receive Buffer Register (RB) ............................................................................................................... 79 7.1.2 Transmit Buffer Register (TB)............................................................................................................... 79 7.1.3 Interrupt Enable Register (IER) ............................................................................................................ 79 7.1.4 Fifo Control Register (FCR) .................................................................................................................. 80 7.1.5 Interrupt Identification Register (IIR)..................................................................................................... 81 7.1.6 Line Control Register (LCR) ................................................................................................................. 82 7.1.7 Modem Control Register (MCR) ........................................................................................................... 83 7.1.8 Line Status Register (LSR) ................................................................................................................... 84 7.1.9 Modem Status Register (MSR)............................................................................................................. 85 7.1.10 Scratchpad Register (SCR) .................................................................................................................. 86 7.1.11 Programmable Baud Rate Generator (And Divisor Latches DLH, DLL)............................................... 86 7.2 FIFO INTERRUPT MODE OPERATION ...................................................................................................... 87 7.3 FIFO POLLED MODE OPERATION ............................................................................................................ 88 7.3.1 Effect Of The Reset on Register File .................................................................................................... 89 7.3.2 NOTES ON SERIAL PORT FIFO MODE OPERATION ....................................................................... 90 7.3.3 TX AND RX FIFO OPERATION ........................................................................................................... 90 8 INFRARED COMMUNICATIONS CONTROLLER (IRCC 2.0) ............................................................................ 92 8.1 IRRX/IRTX PIN ENABLE.............................................................................................................................. 93 8.2 IR REGISTERS - LOGICAL DEVICE 5 ........................................................................................................ 93 8.3 IR DMA CHANNELS ........................................................................................................................................ 93 8.4 IR IRQS......................................................................................................................................................... 94 8.4.1 Software Select Registers A and B....................................................................................................... 94 8.5 IR HALF DUPLEX TIMEOUT ............................................................................................................................... 94 8.6 IRTX OUTPUT PINS DEFAULT........................................................................................................................... 94 9 PARALLEL PORT................................................................................................................................................ 95 9.1 IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES .............................................................. 96 9.1.1 Register Definition ................................................................................................................................ 96 9.2 EXTENDED CAPABILITIES PARALLEL PORT......................................................................................... 102 SMSC DS – LPC47N252 Page 5 Rev. 09/06/2000 5 Page APPENDIX A: HIGH-PERFORMANCE 8051 CYCLE TIMING & INSTRUCTION SET ........................................... 332 APPENDIX B HIGH PERFORMANCE 8051 EXTENDED INTERRUPT UNIT ......................................................... 336 APPENDIX B INTERRUPTS ...................................................................................................................................... 336 Interrupt Processing............................................................................................................................................ 336 Interrupt Masking ................................................................................................................................................ 336 Interrupt Priorities ............................................................................................................................................... 336 Interrupt Sampling .............................................................................................................................................. 336 Interrupt Latency................................................................................................................................................. 336 DUAL DATA POINTERS ............................................................................................................................................... 336 TIMER 2.................................................................................................................................................................... 337 Overview............................................................................................................................................................. 337 16-bit Timer/Counter Mode with Auto-reload...................................................................................................... 337 Baud Rate Generator Mode................................................................................................................................ 337 SPECIAL FUNCTION REGISTERS .................................................................................................................................. 337 DPL1................................................................................................................................................................... 338 CKCON............................................................................................................................................................... 338 MPAGE............................................................................................................................................................... 339 T2CON................................................................................................................................................................ 339 RCAP2L.............................................................................................................................................................. 340 RCAP2H ............................................................................................................................................................. 340 TL2...................................................................................................................................................................... 341 TH2 ..................................................................................................................................................................... 341 EXIF.................................................................................................................................................................... 341 EICON ................................................................................................................................................................ 342 EIE ...................................................................................................................................................................... 343 EIP ...................................................................................................................................................................... 344 SMSC DS – LPC47N252 Page 11 Rev. 09/06/2000 11 Page

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