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PDF LPC2927 Data sheet ( Hoja de datos )

Número de pieza LPC2927
Descripción ARM9 microcontroller
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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LPC2927/2929
ARM9 microcontroller with CAN, LIN, and USB
Rev. 02 — 22 June 2009
Preliminary data sheet
1. General description
The LPC2927/2929 combine an ARM968E-S CPU core with two integrated TCM blocks
operating at frequencies of up to 125 MHz, Full-speed USB 2.0 OTG and device
controller, CAN and LIN, 56 kB SRAM, up to 768 kB flash memory, external memory
interface, three 10-bit ADCs, and multiple serial and parallel interfaces in a single chip
targeted at consumer, industrial, medical, and communication markets. To optimize
system power consumption, the LPC2927/2929 has a very flexible Clock Generation Unit
(CGU) that provides dynamic clock gating and scaling.
2. Features
I ARM968E-S processor running at frequencies of up to 125 MHz maximum.
I Multi-layer AHB system bus at 125 MHz with four separate layers.
I On-chip memory:
N Two Tightly Coupled Memories (TCM), 32 kB Instruction TCM (ITCM), 32 kB Data
TCM (DTCM).
N Two separate internal Static RAM (SRAM) instances; 32 kB SRAM and 16 kB
SRAM.
N 8 kB ETB SRAM also available for code execution and data.
N Up to 768 kB high-speed flash-program memory.
N 16 kB true EEPROM, byte-erasable and programmable.
I Dual-master, eight-channel GPDMA controller on the AHB multi-layer matrix which can
be used with the SPI interfaces and the UARTs, as well as for memory-to-memory
transfers including the TCM memories.
I External Static Memory Controller (SMC) with eight memory banks; up to 32-bit data
bus; up to 24-bit address bus.
I Serial interfaces:
N USB 2.0 full-speed device/OTG controller with dedicated DMA controller and
on-chip device PHY.
N Two-channel CAN controller supporting FullCAN and extensive message filtering.
N Two LIN master controllers with full hardware support for LIN communication. The
LIN interface can be configured as UART to provide two additional UART
interfaces.
N Two 550 UARTs with 16-byte Tx and Rx FIFO depths, DMA support, and
RS485/EIA-485 (9-bit) support.
N Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations deep;
Tx FIFO and Rx FIFO.
N Two I2C-bus interfaces.

1 page




LPC2927 pdf
NXP Semiconductors
5. Pinning information
5.1 Pinning
www.DataSheet4U.com
LPC2927/2929
ARM9 microcontroller with CAN, LIN, and USB
1 108
LPC2927FBD144
LPC2929FBD144
36 73
Fig 2. Pin configuration for SOT486-1 (LQFP144)
002aae144
5.2 Pin description
5.2.1 General description
The LPC2927/2929 uses five ports: port 0 with 32 pins, ports 1 and 2 with 28 pins each,
port 3 with 16 pins, and port 5 with 2 pins. Port 4 is not used. The pin to which each
function is assigned is controlled by the SFSP registers in the SCU. The functions
combined on each port pin are shown in the pin description tables in this section.
5.2.2 LQFP144 pin assignment
Table 3. LQFP144 pin assignment
Pin name
Pin Description
Function 0
(default)
Function 1
TDO
1[1] IEEE 1149.1 test data out
P2[21]/SDI2/
PCAP2[1]/D19
2[1] GPIO 2, pin 21 SPI2 SDI
P0[24]/TXD1/
3[1] GPIO 0, pin 24 UART1 TXD
TXDC1/SCS2[0]
P0[25]/RXD1/
RXDC1/SDO2
4[1] GPIO 0, pin 25 UART1 RXD
P0[26]/TXD1/SDI2 5[1]
GPIO 0, pin 26
-
P0[27]/RXD1/SCK2 6[1]
GPIO 0, pin 27
-
P0[28]/CAP0[0]/ 7[1] GPIO 0, pin 28
MAT0[0]
-
P0[29]/CAP0[1]/ 8[1] GPIO 0, pin 29
MAT0[1]
-
VDD(IO)
P2[22]/SCK2/
PCAP2[2]/D20
9
10[1]
3.3 V power supply for I/O
GPIO 2, pin 22
SPI2 SCK
Function 2
PWM2 CAP1
CAN1 TXD
CAN1 RXD
UART1 TXD
UART1 RXD
TIMER0 CAP0
TIMER0 CAP1
PWM2 CAP2
Function 3
EXTBUS D19
SPI2 SCS0
SPI2 SDO
SPI2 SDI
SPI2 SCK
TIMER0 MAT0
TIMER0 MAT1
EXTBUS D20
LPC2927_29_2
Preliminary data sheet
Rev. 02 — 22 June 2009
© NXP B.V. 2009. All rights reserved.
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LPC2927 arduino
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LPC2927/2929
ARM9 microcontroller with CAN, LIN, and USB
Table 3. LQFP144 pin assignment …continued
Pin name
Pin Description
Function 0
(default)
Function 1
P0[19]/IN2[3]/
PMAT2[1]/A15
133[4] GPIO 0, pin 19
ADC2 IN3
P3[4]/MAT3[2]/
PMAT2[4]/TXDC1
134[1] GPIO 3, pin 4
TIMER3 MAT2
P3[5]/MAT3[3]/
PMAT2[5]/RXDC1
135[1] GPIO 3, pin 5
TIMER3 MAT3
P2[18]/SCS2[1]/
PCAP1[1]/D16
136[1] GPIO 2, pin 18
SPI2 SCS1
P2[19]/SCS2[0]/
PCAP1[2]/D17
137[1] GPIO 2, pin 19
SPI2 SCS0
P0[20]/IN2[4]/
PMAT2[2]/A16
138[4] GPIO 0, pin 20
ADC2 IN4
P0[21]/IN2[5]/
PMAT2[3]/A17
139[4] GPIO 0, pin 21
ADC2 IN5
P0[22]/IN2[6]/
PMAT2[4]/A18
140[4] GPIO 0, pin 22
ADC2 IN6
VSS(IO)
P0[23]/IN2[7]/
PMAT2[5]/A19
141
142[4]
ground for I/O
GPIO 0, pin 23
ADC2 IN7
P2[20]/
PCAP2[0]/D18
143[1] GPIO 2, pin 20
SPI2 SDO
TDI 144[1] IEEE 1149.1 data in, pulled up internally
Function 2
PWM2 MAT1
PWM2 MAT4
PWM2 MAT5
PWM1 CAP1
PWM1 CAP2
PWM2 MAT2
PWM2 MAT3
PWM2 MAT4
PWM2 MAT5
PWM2 CAP0
Function 3
EXTBUS A15
CAN1 TXD
CAN1 RXD
EXTBUS D16
EXTBUS D17
EXTBUS A16
EXTBUS A17
EXTBUS A18
EXTBUS A19
EXTBUS D18
[1] Bidirectional pad; analog port; plain input; 3-state output; slew rate control; 5 V tolerant; TTL with hysteresis; programmable pull-up /
pull-down / repeater.
[2] USB pad.
[3] Analog pad; analog I/O.
[4] Analog I/O pad.
6. Functional description
6.1 Architectural overview
The LPC2927/2929 consists of:
An ARM968E-S processor with real-time emulation support
An AMBA multi-layer Advanced High-performance Bus (AHB) for interfacing to the
on-chip memory controllers
Two DTL buses (an universal NXP interface) for interfacing to the interrupt controller
and the Power, Clock and Reset Control cluster (also called subsystem).
Three ARM Peripheral Buses (APB - a compatible superset of ARM's AMBA
advanced peripheral bus) for connection to on-chip peripherals clustered in
subsystems.
One ARM Peripheral Bus for event router and system control.
LPC2927_29_2
Preliminary data sheet
Rev. 02 — 22 June 2009
© NXP B.V. 2009. All rights reserved.
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