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Número de pieza | MB86292 | |
Descripción | Graphics Display Controller | |
Fabricantes | Fujitsu Media Devices Limited | |
Logotipo | ||
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No Preview Available ! FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-31103-1E
www.DataSheet4U.com
ASSP for Graphics Control
Graphics Display Controller
MB86292
s DESCRIPTION
The MB86292 is an evolved version of the Fujitsu MB86290A graphics controller designed for use in a car
navigation system or amusement equipment. The MB86292 is a graphics display controller with an on-chip
geometry processor and digital video capture facility. It can be connected to FCRAM.
Connecting the MB86292 to FCRAM which has lower latency upon a paging error speeds up the random access
to memory, resulting in faster display and drawing. In addition, integrating the geometry processor reduces the
CPU load, thereby improving the performance of the entire system.
s FEATURES
• Operating frequency : 100 MHz (External clock of 14.32 MHz Max)
• Geometry processor : Capable of executing operations for geometric transformation and surface front/rear
evaluation.
• Memory block : Capable of connecting SDRAM and FCRAM
• Video capture block : Embedded facility to capture digital video images, for example, from TV, capable of easily
implementing “Picture in Picture” and video graphics superimposing.
• Host interface : Enables direct connection to various CPUs (Fujitsu SparcLite, Hitachi SH3/4 or NEC V83x) .
s PACKAGE
(Continued)
256-pin plastic QFP
(FPT-256P-M09)
1 page MB86292
www.DataSheet4U.com
• Host Interface Pins
Pin Name Input/output
Function
MODE0-
MODE2
Input
Host CPU mode/Ready mode select
RESET
Input
Hardware reset
D0-D31
Input/output Host CPU bus data
A2-A24
Input
Host CPU bus address (Connect A24 to MWR in V832 mode.)
BCLKI
Input
Host CPU bus clock
BS
Input
Bus cycle start signal
CS
Input
Chip select signal
RD
Input
Read strobe signal
WE0
Input
D0-D7 write strobe signal
WE1
Input
D8-D15 write strobe signal
WE2
Input
D16-D23 write strobe signal
WE3
Input
D24-D31 write strobe signal
RDY
Output
Tristate
Wait request signal (“0” for wait state with SH3; “1” for wait state with SH4, V832,
or SPARClite)
DREQ
Output DMA request signal (active low with both SH and V832)
DRACK/
DMAAK
Input
DMA request acknowledge signal (Connect this to DMAAK in V832 mode.
Active high with both SH and V832.)
DTACK/TC
Input
DMA transfer strobe signal (Connect this to TC in V832 mode. SH = active high,
V832 = active low)
INT Output Host CPU interrupt signal (SH = active low, V832 = active high)
TESTH
Input
Test signal
Note : The host interface can connect the MB86292 to the SH4 (SH7750) or SH3 (SH7709) from Hitachi Ltd. the
V832 from NEC, or to the SPARClite (MB86833) from Fujitsu without any external circuit in between. (Using
the SRAM interface allows the MB86292 to use another CPU.) The host CPU is set by the MODE0 and
MODE1 pins as shown below.
MODE1 pin
L
L
H
H
MODE0 pin
L
H
L
H
SH3
SH4
V832
SPARClite
CPU Type
Note : The MODE2 pin can be used to set the Ready signal level to be used upon completion of the bus cycle. To
use the MODE2 signal at "H" level, set the software setting to two cycles.
MODE2 pin
L
H
Ready signal mode
Set RDY signal to “Not Ready” level upon completion of bus cycle.
Set RDY signal to “Ready” level upon completion of bus cycle.
5
5 Page MB86292
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s ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Min Max
Unit
Power supply voltage
Input voltage
Output current
VDDL*
VDDH
VI
IO
− 0.5
− 0.5
− 0.5
− 13
3.0
4.0
VDDH + 0.5 ( < 4.0)
+ 13
V
V
mA
Power pin current
Ambient storage temperature
IPOW
Tstg
60
− 55
60
+ 125
mA
°C
* : The PLL power supply is included.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter
Power supply voltage
Input voltage (“H” level)
Input voltage (“L” level)
Ambient operating temperature
* : The PLL power supply is included.
Symbol
VDDL*
VDDH
VIH
VIL
TA
Min
2.3
3.0
2.0
− 0.3
− 40
Value
Typ
2.5
3.3
Max
2.7
3.6
VDDH + 0.3
+ 0.8
+ 85
Unit
V
V
V
°C
Notes : • The VDDL and VDDH power supplies can be turned on or off in either order.
Note, however, that the VDDH voltage must not be applied alone continuously for several seconds.
• Do not input the HSYNC, VSYNC, or EO signal with the power-supply voltage not applied. (See “Input
voltage” in “s ABSOLUTE MAXIMUM RATINGS”.)
• After turning the power on, input a pulse remaining at low level for at least 500 ns to the S pin. Then, set
the S pin to high level and input the RESET signal held at low level for at least 300 µs.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
11
11 Page |
Páginas | Total 25 Páginas | |
PDF Descargar | [ Datasheet MB86292.PDF ] |
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