PDF LPC3240 Data sheet ( Hoja de datos )

Número de pieza	LPC3240
Descripción	(LPC3220 - LPC3250) 16/32-bit ARM Microcontrollers
Fabricantes	NXP Semiconductors
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No Preview Available ! www.DataSheet4U.com LPC3220/30/40/50 16/32-bit ARM microcontrollers; hardware floating-point coprocessor, USB On-The-Go, and EMC memory interface Rev. 01.01 — 1 April 2009 Product data sheet 1. General description The LPC3220/30/40/50 embedded microcontrollers were designed for low power, high performance applications. NXP achieved their performance goals using a 90 nanometer process to implement an ARM926EJ-S CPU core with a vector floating point co-processor and a large set of standard peripherals including USB On-The-Go. The LPC3220/30/40/50 operates at CPU frequencies of up to 266 MHz. The NXP implementation uses a ARM926EJ-S CPU core with a Harvard architecture, 5-stage pipeline, and an integral Memory Management Unit (MMU). The MMU provides the virtual memory capabilities needed to support the multi-programming demands of modern operating systems. The ARM926EJ-S also has a hardware based set of DSP instruction extensions, which includes single cycle MAC operations, and hardware based native Jazelle Java Byte-code execution. The NXP implementation has a 32 kB instruction cache and a 32 kB data cache. For low power consumption, the LPC3220/30/40/50 takes advantage of NXP’s advanced technology development to optimize intrinsic power and uses software controlled architectural enhancements to optimize application based power management. The LPC3220/30/40/50 also includes 256 kB of on-chip static RAM, a NAND flash interface, an Ethernet MAC, an LCD controller that supports STN and TFT panels, and an external bus interface that supports SDR and DDR SDRAM as well as static devices. In addition, the LPC3220/30/40/50 includes a USB 2.0 full-speed interface, seven UARTs, two I2C-bus interfaces, two SPI/SSP ports, two I2S-bus interfaces, two single output PWMs, a motor control PWM, six general purpose timers with capture inputs and compare outputs, a Secure Digital (SD) interface, and a 10-bit Analog-to-Digital Converter (ADC) with a touch screen sense option. 2. Features ARM926EJS processor, running at CPU clock speeds up to 266 MHz Vector Floating Point (VFP) coprocessor. 32 kB instruction cache and a 32 kB data cache. Up to 256 kB of Internal SRAM (IRAM). Selectable boot-up from various external devices: NAND flash, SPI memory, USB, UART, or static memory. 1 page NXP Semiconductors www.DataSheet4U.com 5. Block diagram LPC3220/30/40/50 16/32-bit ARM microcontrollers VFP9 ETB ETM 9 D-CACHE 32 kB ARM 9EJS I-CACHE 32 kB D-SIDE CONTROLLER MMU I-SIDE CONTROLLER DATA INSTRUCTION master layer 0 1 slave port 0 1 2 3 ethernet PHY interface DMA CONTROLLER M0 M1 23 ETHERNET 10/100 MAC 4 USB transceiver interface LCD panel interface 32-bit wide external memory USB OTG LCD CONTROLLER CONTROLLER EXTERNAL 5 6 MEMORY CONTROLLER port 3 port 4 port 0 SRAM ROM AHB 256 kB 16 kB 5 AHB slaves TO APB slaves APB BRIDGE SLC MLC SPI SD SSP I2S NAND NAND × 2 CARD ×2 ×2 6 DMA USB SDRAM ETB ETHERNET LCD 7 32 bit, AHB matrix AHB TO APB BRIDGE APB slaves I2C ×2 register interfaces STANDARD UART × 4 MOTOR CONTROL PWM = Master/Slave connection supported by the multilayer AHB matrix WATCHDOG TIMERS PWM AHB TO TIMER FAB slaves ×6 ×2 APB BRIDGE SYSTEM CONTROL DEBUG KEY SCANNER RTC HS UART ×3 GPIO INTERRUPT CONTROL UART 10-BIT CONTROL ADC/TS 002aae397 Fig 1. Block diagram of LPC3220/30/40/50 LPC3220_30_40_50_1.1 Product data sheet Rev. 01.01 — 1 April 2009 © NXP B.V. 2009. All rights reserved. 5 of 71 5 Page NXP Semiconductors www.DataSheet4U.com LPC3220/30/40/50 16/32-bit ARM microcontrollers Table 4. Pin description …continued Symbol Pin Power supply domain EMC_A[19]/P1[19] K1 VDD_EMC EMC_A[20]/P1[20] J1 VDD_EMC EMC_A[21]/P1[21] J2 VDD_EMC EMC_A[22]/P1[22] J3 VDD_EMC EMC_A[23]/P1[23] J4 VDD_EMC EMC_BLS[0] EMC_BLS[1] EMC_BLS[2] EMC_BLS[3] EMC_CAS EMC_CKE0 EMC_CKE1 EMC_CLK EMC_CLKIN EMC_CS0 EMC_CS1 EMC_CS2 EMC_CS3 EMC_D[0] EMC_D[1] EMC_D[2] EMC_D[3] EMC_D[4] EMC_D[5] EMC_D[6] EMC_D[7] EMC_D[8] EMC_D[9] EMC_D[10] EMC_D[11] EMC_D[12] EMC_D[13] EMC_D[14] EMC_D[15] U14 VDD_EMC T13 VDD_EMC R12 VDD_EMC P12 VDD_EMC R5 VDD_EMC U3 VDD_EMC L2 VDD_EMC T3 VDD_EMC T4 VDD_EMC U13 VDD_EMC R11 VDD_EMC T12 VDD_EMC V15 VDD_EMC U4 VDD_EMC R7 VDD_EMC T5 VDD_EMC U5 VDD_EMC V3 VDD_EMC V4 VDD_EMC T6 VDD_EMC R8 VDD_EMC V5 VDD_EMC U6 VDD_EMC V6 VDD_EMC T7 VDD_EMC U7 VDD_EMC V7 VDD_EMC T8 VDD_EMC U8 VDD_EMC Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O I O O O O I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK Description EMC address bit 19 Port 1 GPIO bit 19 EMC address bit 20 Port 1 GPIO bit 20 EMC address bit 21 Port 1 GPIO bit 21 EMC address bit 22 Port 1 GPIO bit 22 EMC address bit 23 Port 1 GPIO bit 23 Static memory byte lane 0 select Static memory byte lane 1 select Static memory byte lane 2 select Static memory byte lane 3 select SDRAM column address strobe out, active LOW Clock enable out for SDRAM bank 0 Clock enable out for SDRAM bank 1 SDRAM clock out SDRAM clock feedback EMC static memory chip select 0 EMC static memory chip select 1 EMC static memory chip select 2 EMC static memory chip select 3 EMC data bit 0 EMC data bit 1 EMC data bit 2 EMC data bit 3 EMC data bit 4 EMC data bit 5 EMC data bit 6 EMC data bit 7 EMC data bit 8 EMC data bit 9 EMC data bit 10 EMC data bit 11 EMC data bit 12 EMC data bit 13 EMC data bit 14 EMC data bit 15 LPC3220_30_40_50_1.1 Product data sheet Rev. 01.01 — 1 April 2009 © NXP B.V. 2009. All rights reserved. 11 of 71 11 Page

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