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PDF ISL6323A Data sheet ( Hoja de datos )
| Número de pieza | ISL6323A | |
| Descripción | Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane And PVI Uniplane Processors | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
March 23, 2009
ISL6323A
FN6878.0
Monolithic Dual PWM Hybrid Controller
Powering AMD SVI Split-Plane and PVI
Uniplane Processors
The ISL6323A dual PWM controller delivers high efficiency
and tight regulation from two synchronous buck DC/DC
converters. The ISL6323A supports hybrid power control of
AMD processors which operate from either a 6-bit parallel
VID interface (PVI) or a serial VID interface (SVI). The dual
output ISL6323A features a multi-phase controller to support
uniplane VDD core voltage and a single phase controller to
power the Northbridge (VDDNB) in SVI mode. Only the
multi-phase controller is active in PVI mode to support
uniplane VDD only processors.
A precision uniplane core voltage regulation system is
provided by a two-to-four-phase PWM voltage regulator (VR)
controller. The integration of two power MOSFET drivers,
adding flexibility in layout, reduce the number of external
components in the multi-phase section. A single phase PWM
controller with integrated driver provides a second precision
voltage regulation system for the North Bridge portion of the
processor. This monolithic, dual controller with integrated
driver solution provides a cost and space saving power
management solution.
For applications which benefit from load line programming to
reduce bulk output capacitors, the ISL6323A features output
voltage droop. The multi-phase portion also includes
advanced control loop features for optimal transient
response to load apply and removal. One of these features
is highly accurate, fully differential, continuous DCR current
sensing for load line programming and channel current
balance. Dual edge modulation is another unique feature,
allowing for quicker initial response to high di/dt load
transients.
The ISL6323A supports Power Savings Mode by dropping
the number of phases to one when the PSI_L bit is set.
Ordering Information
PART NUMBER
PART
(Note)
MARKING
TEMP.
(°C)
PACKAGE PKG.
(Pb-free) DWG. #
ISL6323ACRZ* ISL6323A CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7
ISL6323AIRZ* ISL6323A IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel
specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Features
• Processor Core Voltage Via Integrated Multi-Phase
Power Conversion
• Configuration Flexibility
- 2-Phase Operation with Internal Drivers
- 3- or 4-Phase Operation with External PWM Drivers
• PSI_L Support with Phase Shedding for Improved
Efficiency at Light Load
• Serial VID Interface Inputs
- Two Wire, Clock and Data, Bus
- Conforms to AMD SVI Specifications
• Parallel VID Interface Inputs
- 6-bit VID input
- 0.775V to 1.55V in 25mV Steps
- 0.375V to 0.7625V in 12.5mV Steps
• Precision Core Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.6% System Accuracy Over-Temperature
- Adjustable Reference-Voltage Offset
• Optimal Processor Core Voltage Transient Response
- Adaptive Phase Alignment (APA)
- Active Pulse Positioning Modulation
• Fully Differential, Continuous DCR Current Sensing
- Accurate Load Line Programming
- Precision Channel Current Balancing
• Variable Gate Drive Bias: 5V to 12V
• Overcurrent Protection
• Multi-tiered Overvoltage Protection
• Selectable Switching Frequency up to 1MHz
• Simultaneous Digital Soft-Start of Both Outputs
• Processor NorthBridge Voltage Via Single Phase
Power Conversion
• Precision Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.6% System Accuracy Over Temperature
• Serial VID Interface Inputs
- Two Wire, Clock and Data, Bus
- Conforms to AMD SVI Specifications
• Overcurrent Protection
• Continuous DCR Current Sensing
• Variable Gate Drive Bias: 5V to 12V
• Simultaneous Digital Soft-Start of Both Outputs
• Selectable Switching Frequency up to 1MHz
• Pb-Free Plus Anneal Available (RoHS Compliant)
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
www.TDaytapSihceaetl4UA.cpomplication - PVI Mode
ISL6323A
FB
COMP
ISEN3+
ISEN3-
PWM3
VSEN
BOOT1
UGATE1
PHASE1
APA
DVC
LGATE1
ISEN1-
ISEN1+
+5V
+5V
VCC
OFS
FS
PVCC1_2
BOOT2
UGATE2
PHASE2
RSET
LGATE2
VID0
VID1/SEL
VID2
ISEN2-
ISEN2+
VID3
VID4
RGND
VID5
NC PWROK
VDDPWRGD ISEN4+
GND
ISEN4-
+12V
PWM4
ISL6323A
OFF
ON
PVCC_NB
EN
BOOT_NB
UGATE_NB
PHASE_NB
LGATE_NB
COMP_NB ISEN_NB-
FB_NB
ISEN_NB+
+12V
+12V
+12V
VDD
CPU
LOAD
+12V
+12V
BOOT1
UGATE1
PHASE1
LGATE1
PWM1
PGND
ISL6614 +12V
VCC
BOOT2 PVCC
UGATE2GND
PHASE2
PWM2
LGATE2
NORTH BRIDGE REGULATOR
DISABLED IN PVI MODE
VDDNB
NB
LOAD
5 FN6878.0
5 Page 
ISL6323A
www.IDSaEtaNSh_eNetB4U-,.cIoSmEN_NB+
These pins are used for differentially sensing the North
Bridge output current. The sensed current is used for
protection and load line regulation if droop is enabled.
Connect ISEN_NB- to the node between the RC sense
element surrounding the inductor. Tie the ISEN_NB+ pin to
the VNB side of the sense capacitor.
UGATE_NB
Connect this pin to the corresponding upper MOSFET gate.
This pin provides the PWM-controlled gate drive for the
upper MOSFET and is monitored for shoot-through
prevention purposes.
BOOT_NB
This pin provides the bias voltage for the corresponding
upper MOSFET drive. Connect this pin to
appropriately-chosen external bootstrap capacitor. The
internal bootstrap diode connected to the PVCC_NB pin
provides the necessary bootstrap charge.
PHASE_NB
Connect this pin to the source of the corresponding upper
MOSFET. This pin is the return path for the upper MOSFET
drive. This pin is used to monitor the voltage drop across the
upper MOSFET for overcurrent protection.
LGATE_NB
Connect this pin to the corresponding MOSFET’s gate. This
pin provides the PWM-controlled gate drive for the lower
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the lower
MOSFET has turned off.
Operation
The ISL6323A utilizes a multi-phase architecture to provide
a low cost, space saving power conversion solution for the
processor core voltage. The controller also implements a
simple single phase architecture to provide the Northbridge
voltage on the same chip.
Multi-phase Power Conversion
Microprocessor load current profiles have changed to the
point that the advantages of multi-phase power conversion
are impossible to ignore. The technical challenges
associated with producing a single-phase converter that is
both cost-effective and thermally viable have forced a
change to the cost-saving approach of multi-phase. The
ISL6323A controller helps simplify implementation by
integrating vital functions and requiring minimal external
components. The “Controller Block Diagram” on page 3
provides a top level view of the multi-phase power
conversion using the ISL6323A controller.
Interleaving
The switching of each channel in a multi-phase converter is
timed to be symmetrically out of phase with each of the other
channels. In a 3-phase converter, each channel switches 1/3
cycle after the previous channel and 1/3 cycle before the
following channel. As a result, the three-phase converter has
a combined ripple frequency three times greater than the
ripple frequency of any one phase. In addition, the peak-to-
peak amplitude of the combined inductor currents is reduced
in proportion to the number of phases (Equations 2 and 3).
Increased ripple frequency and lower ripple amplitude mean
that the designer can use less per-channel inductance and
lower total output capacitance for any performance
specification.
Figure 1 illustrates the multiplicative effect on output ripple
frequency. The three channel currents (IL1, IL2, and IL3)
combine to form the AC ripple current and the DC load
current. The ripple component has three times the ripple
frequency of each individual channel current. Each PWM
pulse is terminated 1/3 of a cycle after the PWM pulse of the
previous phase. The peak-to-peak current for each phase is
about 7A, and the DC components of the inductor currents
combine to feed the load.
IL1 + IL2 + IL3, 7A/DIV
IL3, 7A/DIV
PWM3, 5V/DIV
IL2, 7A/DIV
IL1, 7A/DIV
PWM2, 5V/DIV
PWM1, 5V/DIV
1μs/DIV
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS
FOR 3-PHASE CONVERTER
To understand the reduction of ripple current amplitude in the
multi-phase circuit, examine Equation 2, which represents
an individual channel peak-to-peak inductor current.
IPP =
(---V----I--N-----–-----V----O-----U----T---)----V----O----U-----T-
L fS VIN
(EQ. 2)
In Equation 2, VIN and VOUT are the input and output
voltages respectively, L is the single-channel inductor value,
and fS is the switching frequency.
The output capacitors conduct the ripple component of the
inductor current. In the case of multi-phase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 2 to the
expression for the peak-to-peak current after the summation
of N symmetrically phase-shifted inductor currents in
Equation 3. Peak-to-peak ripple current decreases by an
amount proportional to the number of channels. Output-
voltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple
11 FN6878.0
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ISL6323A.PDF ] | |
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