PDF SII3132 Data sheet ( Hoja de datos )

Número de pieza	SII3132
Descripción	PCI Express to Serial ATA Controller
Fabricantes	Silicon image
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SiI-DS-0138-C Revision C 02 Feb 2007 SiI3132 PCI Express to Serial ATA Controller www.DataSheet4U.com Data Sheet Silicon Image, Inc. 1060 East Arques Ave. Sunnyvale CA 94085 (408) 616-4000 www.siliconimage.com 1 page 7.3.9 Port Command Execution FIFO .........................................................................................................................72 7.3.10 Port Command Error ..........................................................................................................................................73 7.3.11 Port FIS Configuration ........................................................................................................................................75 7.3.12 Port PCI Express Request FIFO Threshold........................................................................................................76 7.3.13 Port 8B/10B Decode Error Counter ....................................................................................................................76 7.3.14 Port CRC Error Counter .....................................................................................................................................77 7.3.15 Port Handshake Error Counter ...........................................................................................................................77 7.3.16 Port PHY Configuration ......................................................................................................................................78 7.3.17 Port Device Status Register ...............................................................................................................................79 7.3.18 Port Device QActive Register .............................................................................................................................79 7.3.19 Port Context Register .........................................................................................................................................80 7.3.20 SControl .............................................................................................................................................................81 7.3.21 SStatus...............................................................................................................................................................82 7.3.22 SError .................................................................................................................................................................83 7.3.23 SActive ...............................................................................................................................................................83 7.3.24 SNotification .......................................................................................................................................................84 7.4 Internal Register Space – Base Address 2 ........................................................................................... 84 7.4.1 Global Register Offset ........................................................................................................................................84 7.4.2 Global Register Data ..........................................................................................................................................84 7.4.3 Port Register Offset ............................................................................................................................................85 7.4.4 Port Register Data ..............................................................................................................................................85 www.DataS8heePt4oUw.ceor mManagement........................................................................................................................86 9 Flash, GPIO, EEPROM, and I2C Programming.............................................................................87 9.1 Flash Memory Access ............................................................................................................................ 87 9.1.1 PCI Direct Access...............................................................................................................................................87 9.1.2 Register Access .................................................................................................................................................87 9.2 I2C Operation ........................................................................................................................................... 88 Data Sheet Rev C 02/02/07 Copyright © 2006 Silicon Image Inc. 5 5 Page 2.2 SATA Interface Timing Specifications Symbol TTX_RISE_FALL TTX_TOL_FREQ Parameter Rise and Fall time at transmitter Tx Frequecny Long Term Stability TTX_AC_FREQ Tx Spread-Sprectrum Modulation Deviation TTX_SKEW Tx Differential Skew Condition 20%-80% at Gen 1 20%-80% at Gen 2 CLKI = SSC AC modulation, subject to the "Downspread SSC" triangular modulation (30- 33KHz) profile per 6.6.4.5 in SATA 1.0 specification Min 100 67 -350 -5000 Limits Typ Table 2-5 SATA Interface Timing Specifications 2.3 SATA Interface Transmitter Output Jitter Characteristics Max 273 136 +350 +0 15 Unit ps ppm ppm ps www.DataSheSeyt4mUb.oclom TJ5UI_15G DJ5UI_15G TJ250UI_15G DJ250UI_15G Parameter Total Jitter, Data-Data 5UI Deterministic Jitter, Data- Data 5UI Total Jitter, Data-Data 250UI Deterministic Jitter, Data- Data 250UI Condition Measured at Tx output pins peak to peak phase variation Random data pattern Measured at Tx output pins peak to peak phase variation Random data pattern Measured at Tx output pins peak to peak phase variation Random data pattern Measured at Tx output pins peak to peak phase variation Random data pattern Limits Min Typ 80 40 100 60 Table 2-6 SATA Interface Transmitter Output Jitter Characteristics, 1.5 Gb/s Symbol Parameter TJfBAND/10_3G Total Jitter, fC3dB=fBAUD/10 DJfBAND/10_3G Deterministic Jitter, fC3dB=fBAUD/10 TJfBAND/500_3G Total Jitter, fC3dB=fBAUD/500 DJfBAND/500_3G Deterministic Jitter, fC3dB=fBAUD/500 Condition Measured at SATA Compliance Point Random data pattern Load = LL Laboratory Load Measured at SATA Compliance Point Random data pattern Load = LL Laboratory Load Measured at SATA Compliance Point Random data pattern Load = LL Laboratory Load Measured at SATA Compliance Point Random data pattern Load = LL Laboratory Load Limits Min Typ 60 15 70 20 Table 2-7 SATA Interface Transmitter Output Jitter Characteristics, 3 Gb/s Max Max Unit ps ps ps ps Unit ps ps ps ps Data Sheet Rev C 02/02/07 Copyright © 2006 Silicon Image Inc. 11 11 Page

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