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PDF MB91F128 Data sheet ( Hoja de datos )
| Número de pieza | MB91F128 | |
| Descripción | (MB91F127 / MB91F128) 32-Bit Microcontroller CMOS | |
| Fabricantes | Fujitsu Media Devices | |
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FUJITSU SEMICONDUCTOR
DATA SHEET
32-Bit Microcontroller
CMOS
FR30 Series
MB91F127/F128
DS07-16310-1E
s DESCRIPTION
This model, designed on the basis of 32-bit RISC CPU (FR30 series), is a standard single-chip micro controller
with built-in I/O resources and bus control functions. The functions are suitable for built-in control that requires
high-speed CPU processing.
MB91F127 includes 256 Kbytes built-in flash memory and 14 Kbytes built-in RAM. MB91F128 includes 510 Kbytes
built-in flash memory and 14 Kbytes built-in RAM.
The specifications of the devices are best suited for applications requiring high-level CPU processing capabilities,
such as navigation system, high-performance FAX, and printer controller.
s FEATURES
FR-CPU
• 32-bit RISC (FR30), load/store architecture, 5-step pipeline
• Operating frequency : Internal 25 MHz
• General register : 32bit x 16 registers
• 16-bit fixed-length instructions (primitives), 1 instruction/1 cycle
• Instructions of memory-to-memory transfer, bit processing, and barrel shift : Instructions suitable for built-in
control
s PACKAGE
(Continued)
100 pin, Plastic LQFP
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(FPT-100P-M05)
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MB91F127/F128
s PIN DESCRIPTION
Note that the numbers in the table are not pin numbers on a package.
No.
Pin name
Input/output
circuit type
Description
1 D16/P20
2 D17/P21
3 D18/P22
4 D19/P23
5 D20/P24
6 D21/P25
7 D22/P26
8 D23/P27
Bit 16 through bit 23 of external data bus.
D
The terminals are available as general I/O ports (P20 through
P27) when external bus width is specified at 8 bits or in single-
chip mode.
9 D24/P30
10 D25/P31
11 D26/P32
12 D27/P33
13 D28/P34
14 D29/P35
15 D30/P36
16 D31/P37
Bit 24 through bit 31 of external data bus.
D The terminals are available as general I/O ports (P30 through
P37) when the terminals are not used.
17 A00/P40
18 A01/P41
19 A02/P42
20 A03/P43
21 A04/P44
22 A05/P45
23 A06/P46
24 A07/P47
25 A08/P50
26 A09/P51
27 A10/P52
28 A11/P53
29 A12/P54
30 A13/P55
31 A14/P56
32 A15/P57
Bit 00 through bit 15 of external address bus.
D
The terminals are available as general I/O ports (P40 through
P47 and P50 through P57) when the terminals are not used as
address buses.
33 A16/P60
34 A17/P61
35 A18/P62
36 A19/P63
37 A20/P64
38 A21/P65
39 A22/P66/IN2
40 A23/P67/IN3
Bit 16 through bit 23 of external address bus.
The terminals are available as general I/O ports (P60 through
D P67) when the terminals are not used as address busses.
[IN2,IN3]: Input terminals of input capture.
This function is active when input capture is operating.
(Continued)
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MB91F127/F128
5. Connecting power supply terminals (VCC, VSS)
If two or more VCC, VSS terminals are used, the terminals to be placed under the same potentials are connected
with each other internally for preventing malfunctions such as latch up. However, for reducing unwanted radiation,
preventing malfunctions of strobe signals and observing total power and current ratings, be sure to connect all
of these terminals to power supply and ground externally.
Connecting power supply to VCC - VSS in impedance as low as possible is desirable.
6. Crystal oscillator circuit
Noises around X0 and X1 terminals causes malfunction of the device. Design printed wiring so that X0, X1,
and crystal oscillator (or ceramic oscillator), and bypass capacitor to the ground are aligned as close as possible
one another. Also the wiring of those elements should not cross with other wiring if possible. Printed wiring
with ground wires around X0 and X1 terminals ensures more stable operations. Such designing is strongly
recommended.
7. Treating NC terminals
Be sure to leave NC terminals open.
8. Mode terminals (MD0 through MD2)
Do not connect the mode terminals directly to VCC or VSS.
For preventing malfunctions caused by noises, make printed traces between the mode terminals and VCC or
VSS as short as possible, and connect the elements in lower impedance.
9. Turning power on
Be sure to turn on the power of the device with RST terminal placed under "L" level. Ensure a period at a
minimum of 5 cycles of internal operation clock before placing the terminal under "H" level.
10. Terminal status upon turning on power
Status upon turning on the power is indefinite. Upon turning on the power, oscillation starts and the circuit is
initialized.
11. Oscillation input upon turning on power
Upon turning on the power, be sure to input a clock signal until oscillation stabilizing wait status is released.
12. Initializing power-on reset
The device includes some built-in registers that are initialized only with power-on reset operation. For initializing
the registers, perform power-on reset by turning on the power again.
13. Recovery from Sleep/Stop status
For recovering from Sleep/Stop status initiated by a program in C-Bus RAM, reset the device instead of
recovering by an interrupt process.
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MB91F128.PDF ] | |
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