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PDF LTC1702I Data sheet ( Hoja de datos )
| Número de pieza | LTC1702I | |
| Descripción | Dual 550kHz Synchronous 2-Phase Switching Regulator Controller | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC1702
Dual 550kHz Synchronous
2-Phase Switching Regulator Controller
FEATURES
s Two Independent Controllers in One Package
s Two Sides Run Out-of-Phase to Minimize CIN
s All N-Channel External MOSFET Architecture
s No External Current Sense Resistors
s Excellent Output Regulation: 1% Total Output
Accuracy
s 550kHz Switching Frequency Minimizes External
Component Size
s 1A to 25A Output Current per Channel
s High Efficiency over Wide Load Current Range
s Quiescent Current Drops Below 100µA in Shutdown
s Small 24-Pin Narrow SSOP Package
U
APPLICATIO S
s Microprocessor Core and I/O Supplies
s Multiple Logic Supply Generator
s Distributed Power Applications
s High Efficiency Power Conversion
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a trademark of Linear Technology Corporation.
DESCRIPTIO
The LTC®1702 is a dual switching regulator controller opti-
mized for high efficiency with low input voltages. It includes
two complete, on-chip, independent switching regulator
controllers each designed to drive a pair of external N-channel
MOSFET devices in a voltage mode feedback, synchronous
buck configuration. The LTC1702 uses a constant-frequency,
true PWM design switching at 550kHz, minimizing external
component size and cost and maximizing load transient
performance. The synchronous buck architecture automati-
cally shifts to discontinuous and then to Burst ModeTM
operation as the output load decreases, ensuring maximum
efficiency over a wide range of load currents.
The LTC1702 features an onboard reference trimmed to
0.5% and can provide better than 1% regulation at the
converter outputs. Open-drain logic outputs indicate whether
either output has risen to within 5% of the final output voltage
and an optional latching FAULT mode protects the load if the
output rises 15% above the intended voltage. Each channel
can be enabled independently; with both channels disabled,
the LTC1702 shuts down and supply current drops below
100µA.
TYPICAL APPLICATIO
Dual Output High Power 3.3V/2.5V Logic Supply
COUT1, COUT2: PANASONIC EEFUE0G181R
CIN: KEMET TS10X337M010AS
D1, D2: MOTOROLA MBR0520LT1
D3, D4: MOTOROLA MBRS320T3
L1, L2: SUMIDA CEP125-1R0
Q1 TO Q8: FAIRCHILD FDS6670A
1µF
VOUT1
2.5V
AT 15A
Q1
L1
1µH
+
1µF
COUT1
180µF
×4
D3
1.2k
Q3
10k 820pF
1%
Q2
Q4
VIN
PWRGD1
10k
4.75k
1%
47k
680pF
27pF
VIN = 5V ±10%
D2 10Ω 10µF
1µF
1
1µF PVCC
2
BOOST1
24
IMAX2
23
BOOST2
3
BG1
22
BG2
4
TG1
21
TG2
5 20
SW1 SW2
27k 6
19
IMAX1
7
LTC1702
PGND
18
PGOOD1
PGOOD2
8
FCB
17
FAULT
9
RUN/SS
1µF 10
COMP1
16
RUN/SS2
15
COMP2
11
SGND
14
FB2
12
FB1
13
VCC
+
D1
27k
CIN
330µF
×3
10µF
1µF
27pF
1µF
Q5 Q6
L2
1µH
Q7 Q8 D4
VOUT2
3.3V/15A
1.6k
680pF
15.8k + COUT2
1% 180µF
×4
1µF
68k
3300pF
4.99k
1%
VIN
10k
PWRGD2
FAULT
1702 TA01
1
1 page  
LTC1702
PIN FUNCTIONS
PVCC (Pin 1): Driver Power Supply Input. PVCC provides
power to the two BGn output drivers. PVCC must be
connected to a voltage high enough to fully turn on the
external MOSFETs QB1 and QB2. PVCC should generally
be connected directly to VIN. PVCC requires at least a 1µF
bypass capacitor directly to PGND.
BOOST1 (Pin 2): Controller 1 Top Gate Driver Supply. The
BOOST1 pin supplies power to the floating TG1 driver.
BOOST1 should be bypassed to SW1 with a 1µF capacitor.
An additional Schottky diode from VIN to BOOST1 pin will
create a complete floating charge-pumped supply at
BOOST1. No other external supplies are required.
BG1 (Pin 3): Controller 1 Bottom Gate Drive. The BG1 pin
drives the gate of the bottom N-channel synchronous
switch MOSFET, QB1. BG1 is designed to drive up to
10,000pF of gate capacitance directly. If RUN/SS1 goes
low, BG1 will go low, turning off QB1. If FAULT mode is
tripped, BG1 will go high and stay high, keeping QB1 on
until the power is cycled.
TG1 (Pin 4): Controller 1 Top Gate Drive. The TG1 pin
drives the gate of the top N-channel MOSFET, QT1. The
TG1 driver draws power from the BOOST1 pin and returns
to the SW1 pin, providing true floating drive to QT1. TG1
is designed to drive up to 10,000pF of gate capacitance
directly. In shutdown or fault modes, TG1 will go low.
SW1 (Pin 5): Controller 1 Switching Node. SW1 should be
connected to the switching node of converter 1. The TG1
driver ground returns to SW1, providing floating gate
drive to the top N-channel MOSFET switch, QT1. The
voltage at SW1 is compared to IMAX1 by the current limit
comparator while the bottom MOSFET, QB1, is on.
IMAX1 (Pin 6): Controller 1 Current Limit Set. The IMAX1
pin sets the current limit comparator threshold for
controller 1. If the voltage drop across the bottom MOSFET,
QB1, exceeds the magnitude of the voltage at IMAX1,
controller 1 will go into current limit. The IMAX1 pin has an
internal 10µA current source pull-up, allowing the current
threshold to be set with a single external resistor to PGND.
See the Current Limit Programming section for more
information on choosing RIMAX.
PGOOD1 (Pin 7): Controller 1 Power Good. PGOOD1 is an
open-drain logic output. PGOOD1 will pull low whenever
FB1falls 5% below its programmed value. When RUN/SS1
is low (side 1 shut down), PGOOD1 will go high.
FCB (Pin 8): Force Continuous Bar. The FCB pin forces
both converters to maintain continuous synchronous
operation regardless of load when the voltage at FCB
drops below 0.8V. FCB is normally tied to VCC. To force
continuous operation, tie FCB to SGND. FCB can also be
connected to a feedback resistor divider from a secondary
winding on one converter’s inductor to generate a third
regulated output voltage. Do not leave FCB floating.
RUN/SS1 (Pin 9): Controller 1 Run/Soft-start. Pulling
RUN/SS1 to SGND will disable controller 1 and turn off
both of its external MOSFET switches. Pulling both
RUN/SS pins down will shut down the entire LTC1702,
dropping the quiescent supply current below 100µA. A
capacitor from RUN/SS1 to SGND will control the turn-on
time and rate of rise of the controller 1 output voltage at
power-up. An internal 3.5µA current source pull-up at
RUN/SS1 pin sets the turn-on time at approximately
500ms/µF.
COMP1 (Pin 10): Controller 1 Loop Compensation. The
COMP1 pin is connected directly to the output of the first
controller’s error amplifier and the input to the PWM
comparator. An RC network is used at the COMP1 pin to
compensate the feedback loop for optimum transient
response.
SGND (Pin 11): Signal Ground. All internal low power
circuitry returns to the SGND pin. Connect to a low
impedance ground, separated from the PGND node. All
feedback, compensation and soft-start connections should
return to SGND. SGND and PGND should connect only at
a single point, near the PGND pin and the negative plate of
the CIN bypass capacitor.
FB1 (Pin 12): Controller 1 Feedback Input. FB1 should be
connected through a resistor network to VOUT1 to set the
output voltage. The loop compensation network for con-
troller 1 also connects to FB1.
VCC (Pin 13): Power Supply Input. All internal circuits
except the output drivers are powered from this pin. VCC
should be connected to a low noise power supply voltage
between 3V and 7V and should be bypassed to SGND with
at least a 1µF capacitor in close proximity to the LTC1702.
5
5 Page 
LTC1702
APPLICATIONS INFORMATION
improves loop phase margin (see Figure 3). The Feedback
Loop/Compensation section contains a detailed explana-
tion of type 3 feedback loops.
COMP
R2
+
FB
–
0.8V
FB
C2
C1
C3
R3
R1
RB
VOUT
1702 F03
Notice that the FB pin is the virtual ground node of the
feedback amplifier. A typical compensation network does
not include local DC feedback around the amplifier, so that
the DC level at FB will be an accurate replica of the output
voltage, divided down by R1 and RB (Figure 3). However,
the compensation capacitors will tend to attenuate AC
signals at FB, especially with low bandwidth type 1 feed-
back loops. This creates a situation where the MIN and
MAX comparators do not respond immediately to shifts in
the output voltage, since they monitor the output at FB.
Maximizing feedback loop bandwidth will minimize these
delays and allow MIN and MAX to operate properly. See
the Feedback Loop/Compensation section.
Figure 3. “Type 3” Feedback Loop
MIN/MAX
Two additional feedback loops keep an eye on the primary
feedback amplifier and step in if the feedback node moves
±5% from its nominal 800mV value. The MAX comparator
(see Block Diagram) activates whenever FB rises more
than 5% above 800mV. It immediately turns the top
MOSFET (QT) off and the bottom MOSFET (QB) on and
keeps them that way until FB falls back within 5%. This
pulls the output down as fast as possible, preventing
damage to the (often expensive) load. If FB rises because
the output is shorted to a higher supply, QB will stay on
until the short goes away, the higher supply current limits
or QB dies trying to save the load. This behavior provides
maximum protection against overvoltage faults at the
output, while allowing the circuit to resume normal opera-
tion when the fault is removed. The overvoltage protection
circuit can optionally be set to latch the output off perma-
nently (see the Overvoltage Fault section).
The MIN comparator (see Block Diagram) trips whenever
FB is more than 5% below 800mV and immediately forces
the switch duty cycle to 90% to bring the output voltage
back into range. It releases when FB is within the 5%
window. MIN is disabled when the soft-start or current
limit circuits are active—the only two times that the
output should legitimately be below its regulated value.
PGOOD Flags
The MIN comparator performs another function; it drives
the external “power good” pin (PGOOD) through a 100µs
delay stage. PGOOD is an open-drain output, allowing it to
be wire-OR’ed with other open-drain/open-collector sig-
nals. An external pull-up resistor is required for PGOOD to
swing high. Any time the FB pin is more than 5% below the
programmed value for more than 100µs, PGOOD will pull
low, indicating that the output is out of regulation. PGOOD
remains active during soft-start and current limit, even
though the MIN comparator has no effect on the duty cycle
during these times. The 100µs delay ensures that short
output transient glitches that are successfully “caught” by
the MIN comparator don’t cause momentary glitches at
the PGOOD pin. Note that the PGOOD pin only watches
MIN, not MAX—it does not indicate if the output is 5%
above the programmed value.
When either side of the LTC1702 is in shutdown, its
associated PGOOD pin will go high. This behavior allows
a valid PGOOD reading when the two PGOOD pins are tied
together, even if one side is shut down. It also reduces
quiescent current by eliminating the excess current drawn
by the pull-up at the PGOOD pin. As soon as the RUN/SS
pin rises above the shutdown threshold and the side
comes out of shutdown, the PGOOD pin will pull low until
the output voltage is valid. If both sides are shut down at
the same time, both PGOOD pins will go high. To avoid
confusion, if either side of the LTC1702 is shut down, the
host system should ignore the associated PGOOD pin.
11
11 Page | ||
| Páginas | Total 36 Páginas | |
| PDF Descargar | [ Datasheet LTC1702I.PDF ] | |
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