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PDF AM79C960 Data sheet ( Hoja de datos )
| Número de pieza | AM79C960 | |
| Descripción | PCnetTM-ISA Single-Chip Ethernet Controller | |
| Fabricantes | Advanced Micro Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AM79C960 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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PRELIMINARY
Am79C960
PCnetTM-ISA Single-Chip Ethernet Controller
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
s Single-chip Ethernet controller for the Industry
Standard Architecture (ISA) and Extended
Industry Standard Architecture (EISA) buses
s Supports IEEE 802.3/ANSI 8802-3 and Ethernet
standards
s Direct interface to the ISA or EISA bus
s Software compatible with AMD’s Am7990
LANCE register and descriptor architecture
s Low power, CMOS design with sleep mode
allows reduced power consumption for critical
battery powered applications
s Individual 136-byte transmit and 128-byte
receive FIFOs provide packet buffering for
increased system latency, and support the
following features:
— Automatic retransmission with no FIFO
reload
— Automatic receive stripping and transmit
padding (individually programmable)
— Automatic runt packet rejection
— Automatic deletion of received collision
frames
s Dynamic transmit FCS generation program-
mable on a frame-by-frame basis
s Single +5 V power supply
s Internal/external loopback capabilities
s Supports optional Boot PROM for diskless
node applications
s Provides integrated Attachment Unit Interface
(AUI) and 10BASE-T transceiver with 3 modes
of port selection:
— Automatic selection of AUI or 10BASE-T
— Software selection of AUI or 10BASE-T
— Jumper selection of AUI or 10BASE-T
s Automatic Twisted Pair receive polarity
detection and automatic correction of the
receive polarity
s Supports bus-master and shared-memory
architectures to fit in any PC application
s Supports edge and level-sensitive interrupts
s DMA Buffer Management Unit for reduced CPU
intervention
s Integral DMA controller allows higher
throughput by by-passing the platform DMA
s JTAG Boundary Scan (IEEE 1149.1) test access
port interface for board level production test
s Integrated Manchester Encoder/Decoder
s Supports the following types of network
interfaces:
— AUI to external 10BASE2, 10BASE5,
10BASE-T or 10BASE-F MAU
— Internal 10BASE-T transceiver with Smart
Squelch to Twisted Pair medium
s Supports LANCE General Purpose Serial
Interface (GPSI)
s 120-pin PQFP package
GENERAL DESCRIPTION
The PCnet-ISA controller, a single-chip Ethernet con-
troller, is a highly integrated system solution for the
PC-AT Industry Standard Architecture (ISA ) architec-
ture. It is designed to provide flexibility and compatibility
with any existing PC application. This highly integrated
120-pin VLSI device is specifically designed to reduce
parts count and cost, and addresses applications where
higher system throughput is desired. The PCnet-ISA
controller is fabricated with AMD’s advanced low-power
CMOS process to provide low stand by current for
power sensitive applications.
The PCnet-ISA controller is a DMA-based device with a
dual architecture that can be configured in two different
operating modes to suit a particular PC application. In
the Bus Master Mode all transfers are performed using
the integrated DMA controller. This configuration en-
hances system performance by allowing the PCnet-ISA
controller to bypass the platform DMA controller and di-
rectly address the full 24-bit memory space. The
implementation of Bus Master Mode allows minimum
parts count for the majority of PC applications. The
PCnet-ISA controller can be configured to perform
Shared Memory operations for compatibility with low-
end machines, such as PC/XTs that do not support Bus
Master and high-end machines that require local packet
buffering for increased system latency.
Publication# 16907 Rev. B Amendment /0
Issue Date: May 1994
This document contains information on a product under development at Advanced Micro Devices, Inc.
The information is intended to help you to evaluate this product. AMD reserves the right to change or
discontinue work on this proposed product without notice.
1-343
1 page  
PRELIMINARY
AMD
DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-374
BUS INTERFACE UNIT (BIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-374
DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-374
1. Initialization Block DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-374
2. Descriptor DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-374
3. Burst-Cycle DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-374
BUFFER MANAGEMENT UNIT (BMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-374
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-374
Reinitialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-374
Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-375
Descriptor Rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-375
Descriptor Ring Access Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-375
Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-376
Transmit Descriptor Table Entry (TDTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-377
Receive Descriptor Table Entry (RDTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-378
MEDIA ACCESS CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-379
Transmit and Receive Message Data Encapsulation . . . . . . . . . . . . . . . . . . . . . . . 1-379
Media Access Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-380
MANCHESTER ENCODER/DECODER (MENDEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-382
External Crystal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-382
External Clock Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-382
MENDEC Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-382
Transmitter Timing and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-383
Receive Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-383
Input Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-383
Clock Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-383
PLL Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-384
Carrier Tracking and End of Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-384
Data Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-384
Jitter Tolerance Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-384
Attachment Unit Interface (AUI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-384
Differential Input Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-384
Collision Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-384
TWISTED PAIR TRANSCEIVER (T-MAU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-385
Twisted Pair Transmit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-385
Twisted Pair Receive Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-385
Link Test Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-385
Polarity Detection and Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-385
Twisted Pair Interface Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-386
Collision Detect Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-386
Signal Quality Error (SQE) Test (Heartbeat) Function . . . . . . . . . . . . . . . . . . . . . . 1-386
Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-386
Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-386
EADI™ (External Address Detection Interface™) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-387
Am79C960
1-347
5 Page 
PRELIMINARY
CONNECTION DIAGRAM: BUS MASTER
AMD
DVDD2
TE
APCS
BPCS
LA17
LA18
LA19
DVSS3
LA20
LA21
LA22
LA23
SBHE
SA0
SA1
DVSS4
SA2
SA3
SA4
DVSS10
SA5
SA6
SA7
SA8
DVSS5
SA9
SA10
SA11
DVDD3
SA12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
90 XTAL2
89 AVSS2
88 XTAL1
87 AVDD3
86 TXD+
85 TXP+
84 TXD-
83 TXP-
82 AVDD4
81 RXD+
80 RXD-
79 DVSS12
78 SD15
77 SD7
76 SD14
75 SD6
74 DVSS9
73 SD13
72 SD5
71 SD12
70 SD4
69 DVDD6
68 SD11
67 SD3
66 SD10
65 SD2
64 DVSS8
63 SD9
62 SD1
61 SD8
16907B-3
Am79C960
1-353
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AM79C960.PDF ] | |
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