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PDF MVA60000 Data sheet ( Hoja de datos )
| Número de pieza | MVA60000 | |
| Descripción | 1.4 Micron CMOS Megacell ASICs | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
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MVA60000
MVA60000 Series
1.4 Micron CMOS MEGACELL ASICs
DS5499
ISSUE 3.1
March 1991
GENERAL DESCRIPTION
Very large scale integrated circuits, requiring large RAM and s Up to 80,000 used gates at <9µW/MHz per loaded gate
ROM blocks, often do not suit even high complexity gate
arrays, such as Zarlink Semiconductors' CLA60000 series.
(Fanout=2) allows integration of entire systems.
MVA60000 Megacell ASICs provide RAM, ROM, and PLA s 1.1 micron channel length (1.4 micron drawn) dual layer
macros, optimised for minimum area, which are compiled to
match system requirements exactly. Based on an advanced
CMOS process using stacked contacts and vias to produce
mcells virtually 'transparent' to interconnection routing,
MVA60000 allows systems up to 80,000 gates to be
ointegrated on a single silicon chip.
.cWith ever-decreasing lifecycles many systems need a clear
migration route to higher technology. MVA60000 designs are
fully netlist compatible with 1.4 micron CLA60000 array
Udesigns, which provides a clear path for upgrading systems by
integration of large RAM and ROM blocks, and analog
t4elements. Compatibility extends to Zarlink Semiconductors'
new sub-micron CMOS ASIC products, such as the
eCLA70000 gate array family. Operation over the full military
temperature range is easily achieved, even for complex
edesigns, since Zarlink Semiconductors' process allows a
maximum junction temperature of 150 degrees C.
hFEATURES
Ss High performance with typical gate delays of 700ps
ta(NAND2 Fanout=2).
s Extensive cell libraries: 180 SSI microcells, 100 MSI
aand LSI macrocells, and Compiled paracells (ROM to
.D64K bits, RAM to 16K bits and PLAs) to minimise
design timescales.
metal, silicon gate CMOS process, with double polysili
con option for precision analog design.
s Slew controlled outputs with drivers up to 24mA for bus
driving and other applications.
s Netlist compatible with CLA60000 1.4 micron gate array
(and CLA70000 1.0 micron gate array) cell and macro
libraries which provides an easy upgrade path for all
designs.
s Fully supported by simulation and layout software for
quick design and efficient project management.
s ESD protection up to 2kV.
s Easy implementation of JTAG/BIST test philosophies.
s Epitaxial silicon to eliminate Latch-Up.
s Maximum junction temperature of 150 degrees C
permits operation over full military temperature range.
www www.DataSheet4U.comFigure 1: 'VK' Process Cross-Section
1
1 page  
MVA60000
For initial assessments of feasibility, worst case estimations of path delays can be derived from the typical propagation delays
given for each cell (for a nominal 5 volt supply and 25 degrees C) by applying approximate derating factors which depend on the
temperature and supply voltage the device is expected to experience, and also on processing variations.
* For temperature Zarlink Semiconductors has derived a derating multiplier (Kt) of +0.3% per degree C
* For supply voltage derating, a factor of (Kv) -20% per volt of VDD change should be used.
* For manufacturing variation (Kp), the tolerance is +50%, -30%.
So, for example, the maximum variation on typical propagation delays for commercial grade product will be at a supply voltage
of 4.5 volts and an ambient temperature of 70 degrees C.
tpd (max)
= Kp x Kv x Kt x tpd (typ)
=1.50 x (1+0.20(5.0 - 4.5)) x (1+0.003(70-25)) x tpd(typ)
=1.50 x 1.10 x 1.13 x tpd (typ)
=1.86 x tpd (typ)
The minimum delay, will be at a supply voltage of 5.5 volts and an ambient of 0 degrees C and can be calculated as follows:
tpd (min)
=0.70 x (1-0.20(5.5-5.0)) x (1-0.003(25-0)) x tpd (typ)
=0.70 x 0.90 x 0.93 x tpd (typ)
=0.58 x tpd (typ)
A similar calculation may be done for any voltage and temperature relevant to the application. For example, the performance
derating multiplier for worst case military grade characteristics is 2.15 times (=1.50x1.10x1.30) the commercial typical.
A table of the derating factors for the three standard operating environments is given below.
Product Grade Temperature Range tpd(min)
Commercial:
0 to +70 degrees C
0.58
Industrial:
-40 to +85 degrees C
0.51
Military:
-55 to +125 degrees C
0.48
tpd(max)
1.86
1.95
2.15
The actual path delay also depends on the interconnection loading on each of the gates, and on the size and layout of the chip,
so it is difficult to give accurate guidelines for feasibility purposes. However, experience over many years suggests that the
average interconnection load can be related to the fanout load on each gate. As a 'rule of thumb', for circuit blocks equivalent
to about 2500 random logic gates, the AVERAGE interconnection load is one extra load unit for each load unit of fanout. For a
circuit equivalent to roughly 25000 random logic gates, the AVERAGE interconnection load rises to two extra load units for each
load unit of fanout.
The interconnection loading of large macrocells is totally dependant on the chip layout. To estimate the loading effect of long inter-
macro tracks, an estimate of track length is required. The worst case capacitance of the metal tracks is approximately 0.3pF per
mm length. (This figure applies to the first metal layer. The capacitance per unit length of the second metal layer is about half
this value, but in general inter-macro signals use both metal 1 and metal 2 tracks.)
The tables on the facing page demonstrate the influence of load on propagation delay. The Megacell MVA60000 design manuals
detail the variation of propagation delay with load for each cell. Please contact your local Design Centre for more information,
and full support with performance estimates, system definition, and consultation on all aspects of ASIC design.
5
5 Page 
LOGIC MICROCELLS
MVA60000
MVA60000 MICROCELL LIBRARY
The MICROCELL library actually uses basic cells identical to those in the CLA60000 1.4 micron gate array family
LOGIC MICROCELLS:
Cell Name Description
Cell Count Typical Delay
HADD
SUM
CARRY
FADD
BMF1
BMF2
Half Adder + Inverter
Sum Block
Carry Block + NOR Gate
Full Adder + NOR Gate
Fast Full Adder 1
Fast Full Adder 2
4 2.1ns
4 2.0ns
4 1.7ns
8 1.6ns
6 1.9ns
6 1.8ns
MUX2TO1
MUX4TO1
MUX8TO1
MUXI2TO1
MUXI4TO1
MUXI8TO1
2 to 1 Multiplexer
4 to 1 Multiplexer
8 to 1 Multiplexer
2 to 1 Inverting Multiplexer
4 to 1 Inverting Multiplexer
8 to 1 Inverting Multiplexer
3 1.5ns
6 2.2ns
12 3.0ns
2 1.4ns
4 2.6ns
12 3.1ns
CLKA
2CLKA
CLKAP
CLKAM
CLKB
CLKBP
CLKE1
CLKE2
CLKE3
TM
2TM
BDR
TRID
Basic Clock Driver
Dual Basic Clock Driver
Basic Clock Driver + Inverter
Basic Clock Driver + Inverter
Large Clock Driver + Inverter
Large Clock Driver + Inverter
Clock Driver with Enable
Clock Driver with Enable
Clock Driver with Enable
Buffered Transmission Gate
Transmission Gate for 2 to 1 Multiplexing
Bus Driver
Tri-State Driver
2 0.8ns
3 0.5ns
2 0.8ns
2 0.8ns
4 0.9ns
4 0.9ns
4 1.9ns
4 1.5ns
8 2.0ns
1 0.7ns
1 0.2ns
4 1.7ns
4 1.4ns
DL
DL2
DLRS
DLARS
DF
DFRS
MDF
MDFRS
M3DF
M3DFRS
Data Latch
Data Latch
Data Latch with Set and Reset
Data Latch with Set and Reset
D-Type Flip-Flop
D-Type Flip-Flop with Set and Reset
Multiplexed Master-Slave D-Type Flip-Flop
Multiplexed Master-Slave D-Type Flip-Flop with Set and Reset
3 to1 Multiplexed Master-Slave D-Type Flip-Flop
3 to 1 Multiplexed Master-Slave D-Type Flip-Flop with Set and Reset
2 1.4ns
2 1.4ns
3 1.7ns
4 0.9ns
4 0.8ns
6 0.9ns
6 1.4ns
8 1.7ns
8 0.8ns
10 0.9ns
JK
JKRS
JBARK
JBARKRS
BJBARK
BJBARKRS
BDL
BDLRS
BDLARS
BDF
BDFRS
BMDF
BMDFRS
J K Flip Flop
J K Flip Flop with Set and Reset
JBAR - K Flip Flop
JBAR - K Flip Flop with Set and Reset
Buffered J-K Flip-Flop
Buffered J-K Flip-Flop with Set and Reset
Buffered Data Latch
Buffered Data Latch with Set and Reset
Buffered Data Latch with Set and Reset
Buffered Master-Slave D-Type Flip-Flop
Buffered Master-Slave D-Type Flip-Flop with Set and Reset
Buffered Multiplexed Master-Slave D-Type Flip-Flop
Buffered Multiplexed Master-Slave D-Type Flip-Flop with Set and Reset
8
10
6
8
9
12
4
6
6
6
9
9
12
0.8ns
0.9ns
0.9ns
1.0ns
2.8ns
2.9ns
1.3ns
1.6ns
3.2ns
3.3ns
3.8ns
2.6ns
2.9ns
11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet MVA60000.PDF ] | |
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