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PDF CXL5514P Data sheet ( Hoja de datos )

Número de pieza CXL5514P
Descripción CMOS-CCD 1H Delay Line for PAL
Fabricantes Sony Corporation 
Logotipo Sony Corporation Logotipo



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No Preview Available ! CXL5514P Hoja de datos, Descripción, Manual

CXL5514M/P
CMOS-CCD 1H Delay Line for PAL
Description
The CXL5514M/P are CMOS-CCD delay line ICs
designed for processing video signals. This ICs
provide a 1H delay time for PAL signals including
the external lowpass filter.
Features
Single 5V power supply
Low power consumption
Built-in peripheral circuit
Built-in tripling PLL circuit
Sync tip clamp mode
Absolute Maximum Ratings (Ta = 25°C)
Supply voltage VDD +6
Operating temperature Topr –10 to +60
Storage temperature Tstg –55 to +150
Allowable power dissipation
PD
CXL5514M 350
CXL5514P 480
V
°C
°C
mW
mW
Recommended Operating Range (Ta = 25°C)
VDD 5V ± 5%
Recommended Clock Conditions (Ta = 25°C)
Input clock amplitude
VCLK 0.2 to 1.0Vp-p (0.4Vp-p Typ.)
Clock frequency
fCLK
4.433619MHz
Input clock waveform Sine wave
Block Diagram and Pin Configuration (Top View)
CXL5514M
8 pin SOP (Plastic)
CXL5514P
8 pin DIP (Plastic)
Input Signal Amplitude
VSIG 500mVp-p (Typ.), 575mVp-p (Max.)
(at internal clamp condition)
Functions
848-bit CCD register
Clock driver
Auto-bias circuit
Sync tip clamp circuit
Sample and hold circuit
Tripling PLL circuit
Inverted output
Structure
CMOS-CCD
VDD
VCO OUT
VCO IN
876
CLK
5
Auto-bias circuit
Clamp circuit
CCD
(848 bit)
Output circuit
(S/H 1 bit)
1 23
IN AB OUT
PLL
Timing circuit
Clock driver
Bias circuit A
Bias circuit B
4
VSS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94903-ST

1 page




CXL5514P pdf
CXL5514M/P
–5–

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